Granted Patent B1

US 8,433,977 · App. 12/422,738 · Granted Apr 30, 2013

Abstract

Claims (57)

1. A storage device comprising control circuitry operable to:

receive a write command from a host, wherein the write command comprises a host block and corresponding host block address;

partition the host block into a plurality of sub blocks;

generate a plurality of sub block addresses in response to the host block address, wherein each sub block address corresponds to one of the sub blocks;

generate error detection code (EDC) data for each sub block in response to the sub block and corresponding sub block address;

combine each sub block and corresponding EDC data to generate a plurality of partial codewords; and

write the partial codewords to one or more data sectors corresponding to the sub block addresses, wherein each of the partial codewords does not include a corresponding sub block address.

2. The storage device as recited in claim 1 , wherein the EDC data is generated as cyclical redundancy check (CRC) data.

3. The storage device as recited in claim 1 , wherein each sub block address is generated by appending a plurality of bits to the host block address.

4. The storage device as recited in claim 1 , wherein the control circuitry comprises:

a microprocessor operable to execute a control program; and

a host interface operable to receive the write command from the host and generate the EDC data for each sub block.

5. The storage device as recited in claim 4 , wherein:

the control circuitry further comprises a buffer memory;

the host interface is further operable to store the partial codewords in the buffer memory; and

the control circuitry further comprises an interface operable to:

read each partial codeword from the buffer memory;

generate check data over each sub block within each partial codeword and the corresponding sub block address; and

detect an error by comparing the check data to the corresponding EDC data of each partial codeword.

6. The storage device as recited in claim 1 , wherein the control circuitry is further operable to:

receive a read command from the host, wherein the read command comprises the host block address;

generate the plurality of sub block addresses in response to the host block address;

read the plurality of partial codewords from the plurality of data sectors corresponding to the sub block addresses;

generate check data over each sub block within each partial codeword and the corresponding sub block address; and

detect an error by comparing the check data to the corresponding EDC data of each partial codeword.

7. The storage device as recited in claim 6 , wherein the control circuitry comprises:

a microprocessor operable to execute a control program; and

a host interface operable to receive the read command from the host and generate the check data.

8. The storage device as recited in claim 6 , wherein:

the control circuitry further comprises a buffer memory; and

the control circuitry further comprises an interface operable to:

generate the check data;

detect the error by comparing the check data to the corresponding EDC data of each partial codeword; and

store each partial codeword in the buffer memory.

9. A method of operating a storage device, the storage device comprising a plurality of data sectors, the method comprising the steps of:

receiving a write command from a host, wherein the write command comprises a host block and corresponding host block address;

partitioning the host block into a plurality of sub blocks;

generating a plurality of sub block addresses in response to the host block address, wherein each sub block address corresponds to one of the sub blocks;

generating error detection code (EDC) data for each sub block in response to the sub block and corresponding sub block address;

combining each sub block and corresponding EDC data to generate a plurality of partial codewords; and

writing the partial codewords to the data sectors corresponding to the sub block addresses, wherein each of the partial codewords does not include a corresponding sub block address.

10. The method as recited in claim 9 , wherein the EDC data is generated as cyclical redundancy check (CRC) data.

11. The method as recited in claim 9 , wherein each sub block address is generated by appending a plurality of bits to the host block address.

12. The method as recited in claim 9 , wherein the storage device further comprises a microprocessor operable to execute a control program, and a host interface operable to receive the write command from the host and generate the EDC data for each sub block.

13. The method as recited in claim 12 , wherein the storage device further comprises a buffer memory, the method further comprising the steps of:

storing the partial codewords in the buffer memory;

reading each partial codeword from the buffer memory;

generating check data over each sub block within each partial codeword and the corresponding sub block address; and

detecting an error by comparing the check data to the corresponding EDC data of each partial codeword.

14. The method as recited in claim 9 , further comprising the steps of:

receiving a read command from the host, wherein the read command comprises the host block address;

generating the plurality of sub block addresses in response to the host block address;

reading the plurality of partial codewords from the plurality of data sectors corresponding to the sub block addresses;

generating check data over each sub block within each partial codeword and the corresponding sub block address; and

detecting an error by comparing the check data to the corresponding EDC data of each partial codeword.

15. The method as recited in claim 14 , wherein the storage device further comprises a microprocessor operable to execute a control program, and a host interface operable to receive the read command from the host and generate the check data.

16. The method as recited in claim 14 , wherein the storage device further comprises a buffer memory, further comprising the step of storing each partial codeword in the buffer memory.

Assignments (7)