Alternate clock apparatus and methods for improving radio performance
View Patent ↗An alternate clock apparatus and method configured to reduce noise in selected frequency bands in an electronic device such as a communication device is described. In one embodiment the alternate clock includes a ring oscillator to generate multiple time shifted signals which may then be combined to generate clock signals at alternate frequencies to a primary reference. A resynchronization circuit may be coupled to the ring oscillator to periodically resynchronize the ring oscillator to a reference signal to reduce alternate clock jitter.
1. Apparatus for providing an alternate clock signal, comprising:
a ring oscillator;
a multiplexer coupled to outputs of a plurality of stages of the ring oscillator; and
a control circuit coupled to the multiplexer and configured to select two or more of the outputs of the plurality of stages of the ring oscillator to generate the alternate signal;
wherein the control circuit is configured to select the two or more outputs of the plurality of stages by:
selectively stepping through ones of outputs of the plurality of stages of the ring oscillator responsive to the outputs; and
selecting one or more of the two or more outputs of the plurality of stages based at least in part on said stepping; and
wherein the control circuit is configured to sequentially select two output stages of the two or more output stages to generate the alternate clock signal during each cycle of the alternate clock signal.
2. A method of generating an alternate clock signal, comprising:
generating a plurality of time shifted signals at a first frequency based on an input frequency;
selecting two or more of the time shifted signals; and
generating an alternate clock signal based on said two or more of the time shifted signals,
wherein said alternate clock signal is generated at a frequency that is different than the first frequency;
wherein the two or more time shifted signals are generated by a plurality of stages of a ring oscillator;
wherein the two or more time shifted signals are selected from sequential stages of the ring oscillator to provide the alternate clock signal; and
wherein two of the two or more time shifted signals are sequentially selected during each cycle of the alternate clock signal.
3. A communications device comprising:
a first clock circuit configured to generate a clock signal at a first clock frequency; and
a second clock circuit configured to generate a second clock signal having an alternate clock frequency different from said first clock frequency, said second clock circuit comprising:
a ring oscillator;
a multiplexer coupled to the outputs of a plurality of stages of the ring oscillator; and
a control circuit coupled to the multiplexer to select two or more of the outputs of the plurality of stages of the ring oscillator to generate an the second clock signal;
wherein the control circuit is configured to select the two or more outputs of the plurality of stages by:
selectively stepping through ones of outputs of the plurality of stages of the ring oscillator responsive to the second clock signal output; and
selecting ones of the two or more outputs of the plurality of stages based on said stepping; and
wherein the control circuit is configured to sequentially select two output stages of the two or more output stages to generate the alternate clock signal during each cycle of the second clock signal.