Method of updating IC instruction and data cache
View Patent ↗A method of updating a cache in an integrated circuit is provided. The integrated circuit incorporates the cache, memory and a memory interface connected to the cache and memory. Following a cache miss, the method fetches, using the memory interface, first data associated with the cache miss and second data from the memory, where the second data is stored in the memory adjacent the first data, and updates the cache with the fetched first and second data via the memory interface. The cache includes instruction and data cache, the method performing arbitration between instruction cache misses and data cache misses such that the fetching and updating are performed for data cache misses before instruction cache misses.
1. A method of updating a cache in an integrated circuit, the integrated circuit incorporating the cache, memory and a memory interface connected to the cache and memory, the method comprising the steps of, following a cache miss:
(a) fetching, using the memory interface, first data associated with the cache miss and second data from the memory, the second data being stored in the memory adjacent the first data; and
(b) updating the cache with the fetched first and second data via the memory interface; and
wherein the cache includes instruction and data cache, the method including performing arbitration between instruction cache misses and data cache misses such that steps (a) and (b) are performed for data cache misses before instruction cache misses.
2. A method according to claim 1 , the integrated further comprising a processor connected to the memory interface, the processor being configured to attempt a cache update with the first data upon receiving the first data from the memory interface, the method further comprising the step of preventing the attempted cache update by the processor from being successful, thereby preventing interference with the cache update of step (b).
3. A method according to claim 2 , wherein step (b) is performed in response to the processor attempting to update the cache following step (a).
4. A method according to claim 3 , wherein the memory interface is configured to monitor the processor to determine when it attempts to update the cache following step (a).