Economy precision pulse generator
A system includes an input device, an output device, a mechanical chassis, a printed circuit board, and a semiconductor device. The semiconductor device includes a mechanical package, and a semiconductor die. The semiconductor die includes a semiconductor layer, a plurality of metal layers, a clock distribution network that distributes a clock signal within the die, and an economy precision pulse generating circuit. The economy precision pulse generating circuit includes a pre-charge circuit, a gate-to-the-partial-jam-latch-keeper circuit, a partial-jam-latch-keeper circuit, and a pull-down-against-the-up-keeper circuit. A source clock signal is derived from the clock signal. The source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit. A common storage node is connected to a second input of the logical AND circuit. The logical AND circuit outputs an output pulse. The output pulse is fed back to the pull-down-against-the-up-keeper circuit.
1. An economy precision pulse generating circuit comprising:
a pre-charge circuit;
a gate-to-the-partial-jam-latch-keeper circuit;
a partial-jam-latch-keeper circuit; and
a pull-down-against-the-up-keeper circuit,
wherein a source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit,
a common storage node is connected to a second input of the logical AND circuit,
the logical AND circuit outputs an output pulse, and
the output pulse is fed back to the pull-down-against-the-up-keeper circuit.
2. The economy precision pulse generating circuit of claim 1 , further comprising a plurality of metal layer switches.
3. The economy precision pulse generating circuit of claim 2 , wherein one or more of the metal layer switches selects one of the output pulse or the buffered output pulse to be fed back to the pull-down-against-the-up-keeper circuit.
4. The economy precision pulse generating circuit of claim 2 , wherein one or more of the metal layer switches provides one or more additional inverter devices to the partial-jam-latch-keeper circuit.
5. The economy precision pulse generating circuit of claim 1 , wherein pull-down-against-the-up-keeper circuit is a footless domino configuration.
6. The economy precision pulse generating circuit of claim 1 , wherein the partial-jam-latch-keeper-circuit provides a jam latch up keeping function and a gated down keeping function.
7. The economy precision pulse generating circuit of claim 1 , wherein the output pulse is buffered prior to being fed back to the pull-down-against-the-up-keeper circuit.
8. A semiconductor device comprising:
a semiconductor layer,
a plurality of metal layers,
a clock distribution network that distributes a clock signal within the die, and
an economy precision pulse generating circuit comprising:
a pre-charge circuit;
a gate-to-the-partial-jam-latch-keeper circuit;
a partial-jam-latch-keeper circuit; and
a pull-down-against-the-up-keeper circuit,
wherein a source clock signal is derived from the clock signal,
the source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit,
a common storage node is connected to a second input of the logical AND circuit,
the logical AND circuit outputs an output pulse, and
the output pulse is fed back to the pull-down-against-the-up-keeper circuit.
9. The semiconductor device of claim 8 , further comprising a plurality of metal layer switches.
10. The semiconductor device of claim 9 , wherein one or more of the metal layer switches selects one of the output pulse or the buffered output pulse to be fed back to the pull-down-against-the-up-keeper circuit.
11. The semiconductor device of claim 9 , wherein one or more of the metal layer switches provides one or more additional inverter devices to the partial-jam-latch-keeper circuit.
12. The semiconductor device of claim 8 , wherein pull-down-against-the-up-keeper circuit is a footless domino configuration.
13. The semiconductor device of claim 8 , wherein the partial-jam-latch-keeper-circuit provides a jam latch up keeping function and a gated down keeping function.
14. The semiconductor device of claim 8 , wherein the output pulse is buffered prior to being fed back to the pull-down-against-the-up-keeper circuit.
15. A system comprising:
an input device;
an output device;
a mechanical chassis;
a printed circuit board; and
a semiconductor device comprising:
a mechanical package, and
a semiconductor die,
wherein the semiconductor die comprises:
a semiconductor layer,
a plurality of metal layers,
a clock distribution network that distributes a clock signal within the die, and
an economy precision pulse generating circuit comprising:
a pre-charge circuit;
a gate-to-the-partial-jam-latch-keeper circuit;
a partial-jam-latch-keeper circuit; and
a pull-down-against-the-up-keeper circuit,
wherein a source clock signal is derived from the clock signal,
the source clock signal is provided to a first input of a logical AND circuit, the pre-charge circuit, and the gate-to-the-partial-jam-latch-keeper circuit,
a common storage node is connected to a second input of the logical AND circuit,
the logical AND circuit outputs an output pulse, and
the output pulse is fed back to the pull-down-against-the-up-keeper circuit.
16. The system of claim 15 , further comprising a plurality of metal layer switches.
17. The system of claim 16 , wherein one or more of the metal layer switches selects one of the output pulse or the buffered output pulse to be fed back to the pull-down-against-the-up-keeper circuit.
18. The system of claim 16 , wherein one or more of the metal layer switches provides one or more additional inverter devices to the partial-jam-latch-keeper circuit.
19. The system of claim 15 , wherein pull-down-against-the-up-keeper circuit is a footless domino configuration.
20. The system of claim 15 , wherein the partial-jam-latch-keeper-circuit provides a jam latch up keeping function and a gated down keeping function.
21. The system of claim 15 , wherein the output pulse is buffered prior to being fed back to the pull-down-against-the-up-keeper circuit.