Circuit topology for multiple loads

1. A circuit topology for multiple loads, comprising:

a driving terminal to transmit a driving signal;

a plurality of transmitting lines; and

a plurality of loads operable to receive the driving signal from the driving terminal, the plurality of loads connected to the driving terminal one by one via the plurality of transmitting lines;

wherein two of the plurality of transmitting lines, which are nearest and farthest respectively from the driving terminal, are both greater than widths of the other transmitting lines;

wherein at least one resistor is connected between two adjacent loads, to reduce non-monotonic phenomenon generated by an anterior load of the two adjacent loads;

wherein when the number of the plurality of loads is six, a first resistor is connected between a second near load and a third near load from the driving terminal, a second resistor is connected between the third near load and a fourth near load from the driving terminal.

2. The circuit topology of claim 1 , wherein resistances of the first and second resistors are both 47Ω.

3. The circuit topology of claim 1 , wherein nearest and farthest loads from the driving terminal of the plurality of loads are the most important loads in the plurality of loads, and loads between the nearest and farthest loads are less important loads.

4. The circuit topology of claim 3 , wherein the most important loads are function chips, and wherein the less important loads are detecting elements or connection pins.