IP Library Granted Patent US 8,661,443
Granted Patent B2
US 8,661,443 · App. 12/426,139 · Granted Feb 25, 2014

Scheduling and/or organizing task execution for a target computing platform

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Quick Facts
Patent No.
US 8,661,443
App. No.
12/426,139
Granted
Feb 25, 2014
Kind
B2
Abstract

Techniques are generally described relating to methods, apparatuses and articles of manufactures for scheduling and/or organizing execution of tasks on a computing platform. In various embodiments, the method may include identifying successively one or more critical time intervals, and scheduling and/or organizing task execution for each of the one or more identified critical time intervals. In various embodiments, one or more tasks to be executed may be scheduled to execute based in part on their execution completion deadlines. In various embodiments, organizing one or more tasks to execute may include selecting a virtual operating mode of the platform using multiple operating speeds lying on a convexity energy-speed envelope of the platform. Intra-task delay caused by switching operating mode may be considered. Other embodiments may also be described and/or claimed.

Claims (30)

1. A method to schedule a task to be executed on a computing platform, where the computing platform is capable of operating at two or more operating speeds, the method comprising, by a processor:

generating a convex enclosure curve at least partially based on energy consumptions for the two or more operating speeds on the computing platform;

determining an arrival time of the task;

determining a completion deadline of the task;

determining respective lengths of clock cycles at the two or more operating speeds;

determining a number of clock cycles on the computing platform to complete the task at least partially based on the respective lengths of the clock cycles;

determining a virtual operating speed of the computing platform to perform the task before or on the completion deadline of the task to achieve a particular energy consumption at least partially based on the number of clock cycles to complete the task, wherein the virtual operating speed is achieved by operating the computing platform at a first operating speed for a first specified time and at a second operating speed for a second specified time, wherein the first, virtual and second operating speeds are on the convex enclosure curve and the virtual operating speed is higher than the first operating speed but lower than the second operating speed, wherein the first and second operating speeds of the two or more operating speeds are two closest operating speeds to the virtual operating speed;

determining a delay incurred, where the task is idle during the delay when the computing platform switches between the first operating speed and the second operating speed; and

scheduling the task to be executed on the computing platform at the virtual operating speed having taken into consideration the delay.

2. The method of claim 1 , further comprising determining the delay by determining a power rail capacitance of the computing platform and determining a substrate and well capacitance of the computing platform.

3. The method of claim 1 , further comprising calculating the virtual operating speed at least partially based on the two closest operating speeds in the convex enclosure curve operating for respective periods of time.

4. The method of claim 3 , wherein the virtual operating speed is different from the two closest operating speeds on the convex enclosure curve.

5. The method of claim 1 , further comprising scheduling the task to be executed at least partially based on an energy dissipated when the computing platform switches between operating at the two closest operating speeds on the convex enclosure curve.

6. The method of claim 4 , further comprising scheduling the task to be executed at least partially based on an energy dissipated when the computing platform switches between operating at the two closest operating speeds on the convex enclosure curve.

7. An apparatus effective to schedule a task to be executed on a computing platform, where the computing platform is configured to operate at two or more operating speeds, the apparatus comprising:

a memory, including instructions; and

a processor configured to communicate with the memory, the processor effective to:

generate a convex enclosure curve at least partially based on energy consumptions for the two or more operating speeds on the computing platform;

determine an arrival time of the task;

determine a completion deadline of the task;

determine respective lengths of clock cycles at the two or more operating speeds;

determine a number of clock cycles on the computing platform to complete the task at least partially based on the respective lengths of the clock cycles;

determine a virtual operating speed of the computing platform to perform the task before or on the completion deadline of the task to achieve a particular energy consumption at least partially based on the number of clock cycles to complete the task, wherein the virtual operating speed is achieved by operating the computing platform at a first operating speed for a first specified time and at a second operating speed for a second specified time, wherein the first, virtual and second operating speeds are on the convex enclosure curve and the virtual operating speed is higher than the first operating speed but lower than the second operating speed, wherein the first and second operating speeds of the two or more operating speeds are two closest operating speeds to the virtual operating speed;

determine a delay incurred, where the task is idle during the delay when the computing platform switches between the first operating speed and the second operating speed; and

schedule the task to be executed on the computing platform at the virtual operating speed having taken into consideration the delay.

8. The apparatus of claim 7 , wherein the processor is further effective to determine the delay by a determination of a power rail capacitance of the computing platform and a substrate and well capacitance of the computing platform.

9. The apparatus of claim 7 , wherein the processor is further effective to calculate the virtual operating speed at least partially based on the two closest operating speeds in the convex enclosure curve in operation for respective periods of time.

10. The apparatus of claim 9 , wherein the virtual operating speed is different from the two closest operating speeds on the convex enclosure curve.

11. The apparatus of claim 7 , wherein the processor is further effective to schedule the task to be executed at least partially based on an energy dissipated when the computing platform switches between operation at the two closest operating speeds on the convex enclosure curve.

12. The apparatus of claim 9 , wherein the processor is further effective to schedule the task to be executed at least partially based on an energy dissipated when the computing platform switches between operation at the two closest operating speeds on the convex enclosure curve.

Assignments (5)
SECURITY INTEREST Recorded Jan 29, 2019
From: EMPIRE TECHNOLOGY DEVELOPMENT LLC
To: CRESTLINE DIRECT FINANCE, L.P.
Reel/Frame 048373/0217 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2012
From: ARISTAEUS HERMES, LLC
To: EMPIRE TECHNOLOGY DEVELOPMENT, LLC
Reel/Frame 028819/0179 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 21, 2012
From: POTKONJAK, MIODRAG
To: ARISTAEUS HERMES, LLC
Reel/Frame 028819/0344 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 28, 2012
From: TECHNOLOGY CURRENTS LLC
To: EMPIRE TECHNOLOGY DEVELOPMENT LLC
Reel/Frame 028124/0033 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2011
From: POTKONJAK, MIODRAG
To: TECHNOLOGY CURRENTS LLC
Reel/Frame 025675/0657 →