System and method for providing compact mapping between dissimilar memory systems
View Patent ↗A memory mapping system for compactly mapping dissimilar memory systems and methods for manufacturing and using same. The mapping system maps a source memory system into a destination memory system by partitioning the source memory system and disposing memory contents within the partitioned source memory system into the destination memory system. In one embodiment, the mapping system factorizes a source data width of the source memory system in terms of a destination data width of the destination memory system to form at least one data sub-width. A source memory sub-region is defined for each data sub-width. The memory contents associated with each source memory sub-region are disposed within the destination memory system in a side-by-side manner across selected destination memory registers of the destination memory system. The mapping system thereby can compactly map the memory contents into the destination memory system without a loss of valuable memory space.
1. A hardware emulation system for verifying electronic circuit designs including a design memory system having a design memory depth that comprises a predetermined number of design memory registers and a design data width that includes a preselected quantity of design data bits that can be stored in each of the design memory registers, comprising:
a emulation memory system having a emulation memory depth that comprises a predetermined number of emulation memory registers and a emulation data width including a preselected power-of-two quantity of emulation data bits; and
a compiler system that maps the design memory system to said emulation memory system by:
factorizing the design data width of the design memory system to form a plurality of design memory sub-regions having respective sub-region memory depths that are equal to the design memory depth and respective sub-region data widths that include respective portions of the design data bits, the design data width being spanned by said sub-region data widths, said respective sub-region data widths being equal to said emulation data width divided by respective predetermined integer values; selecting a selected design memory sub-region with a selected sub-region memory depth and a selected sub-region data width that is equal to said emulation data width divided by a selected integer value;
identifying sub-region register contents within the design memory registers, said sub-region register contents comprising memory contents within the design memory registers that are associated with the selected design memory sub-region;
dividing said selected sub-region memory depth into a plurality of sub-region memory depth groups each including the selected integer value of the design memory registers; and
storing said sub-region register contents associated with each respective sub-region memory depth group in a side-by-side manner across a selected emulation memory register of said emulation memory system.
2. The hardware emulation system of claim 1 , wherein said design memory system includes at least one design memory instance, and said compiler system maps each of the at least one design memory instance into said emulation memory system.
3. The hardware emulation system of claim 1 , wherein the design memory system is provided as a multiport memory system comprising a port chain of at least one read port and at least one write port.
4. The hardware emulation system of claim 3 , wherein at least one of the at least one read port of the multiport memory system is provided as a read port memory primitive.
5. The hardware emulation system of claim 3 , wherein at least one of the at least one read port of the multiport memory system is provided as a write port memory primitive.
6. The hardware emulation system of claim 1 , wherein said emulation data width of said emulation memory system is selected from a group consisting of a thirty-two bit data width and a sixty-four bit data width.
7. A method for mapping a design memory system within an electronic circuit design into an emulation memory system of a hardware emulation system, the design memory having a design memory depth that comprises a predetermined number of design memory registers and a design data width, the emulation memory system having a emulation memory depth that comprises a predetermined number of emulation memory registers and a emulation data width including a preselected power-of-two quantity of emulation data bits, said method comprising:
compiling the electronic circuit design including mapping the design memory system into the emulation memory system by:
selecting a design register portion within each of the design memory registers, each of said design register portions having a sub-region data width that is equal to the emulation data width divided by a predetermined power-of-two integer value; and
mapping at least one of said design register portions in a side-by-side manner across a selected emulation memory register of the emulation memory system; and
emulating the electronic circuit design including transferring memory contents associated with the design memory system into the emulation memory system in accordance with said mapping the design memory system at run time.
8. A hardware emulation system for verifying an electronic circuit design that includes a design memory system having a design memory depth that comprises a predetermined number of design memory registers and a design data width that includes a preselected quantity of design data bits that can be stored in each of the design memory registers, comprising:
a emulation memory system having a emulation memory depth that comprises a predetermined number of emulation memory registers and a emulation data width including a preselected power-of-two quantity of emulation data bits; and
a compiler system that compiles the electronic circuit design and maps the design memory system into the emulation memory system by:
selecting a design register portion within each of the design memory registers, each of said design register portions having a sub-region data width that is equal to the emulation data width divided by a predetermined power-of-two integer value; and
mapping at least one of said design register portions in a side-by-side manner across a selected emulation memory register of the emulation memory system, wherein the hardware emulation system emulates the electronic circuit design by transferring memory contents associated with the design memory system into the emulation memory system in accordance with said mapping the design memory system at run time.