IP Library Granted Patent US 8,018,957
Granted Patent B2
US 8,018,957 · App. 12/426,529 · Granted Sep 13, 2011

Gateway system with automatic dispatch mechanism and method thereof

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Quick Facts
Patent No.
US 8,018,957
App. No.
12/426,529
Granted
Sep 13, 2011
Kind
B2
Abstract

The method for automatically dispatching frames applied to a gateway comprises the steps of: using a first transceiver module to receive a plurality of frames from a network system; storing the frames in corresponding dispatch registers if at least a portion of the bits of the frames match one of a plurality of predetermined values; scheduling a dispatch order of the dispatch registers in accordance with a dispatch request; and dispatching frames stored in the dispatch registers to a second transceiver module in accordance with the dispatch order.

Claims (22)

1. A gateway system with automatic dispatch mechanism, comprising:

a first transceiver module connected to a first network system;

a second transceiver module connected to a second network system;

a first automatic dispatch module configured to automatically dispatch first frames from the first transceiver module to the second transceiver module, wherein at least a portion of the bits of the first frames match one of a plurality of predetermined values, wherein the first automatic dispatch module comprises:

a plurality of first filters, each of the first filters corresponding to one of a plurality of predetermined values and outputting frames received from the first transceiver module;

a plurality of first dispatch registers configured to store outputs of the plurality of the first filters;

a first dispatch requesting processor configured to schedule dispatch requests from the first dispatch registers; and

a first multiplexer configured to receive frames from the first dispatch register and to output frames to the second transceiver module in accordance with the first dispatch requesting processor;

a second automatic dispatch module configured to automatically dispatch second frames from the second transceiver module to the first transceiver module, wherein at least a portion of the bits of the second frames match one of a plurality of predetermined values, wherein the second automatic dispatch module comprises:

a plurality of second filters, each of the second filters corresponding to one of a plurality of predetermined values and outputting frames from the second transceiver module;

a plurality of second dispatch registers configured to store outputs of the plurality of the second filters;

a second dispatch requesting processor configured to schedule dispatch requests from the second dispatch registers; and

a second multiplexer configured to receive frames from the second dispatch registers and to output frames to the first transceiver module in accordance with the second dispatch requesting processor; and

a main processor configured to control the first transceiver module, the second transceiver module, the first automatic dispatch module and the second automatic dispatch module.

2. The gateway system of claim 1 , wherein the first automatic dispatch module regularly dispatches first frames to the second transceiver module.

3. The gateway system of claim 1 , wherein the second automatic dispatch module regularly dispatches second frames to the first transceiver module.

4. The gateway system of claim 1 , wherein the first automatic dispatch module further comprises a plurality of first timers, and the first timers are configured to control the first dispatch registers to regularly output frames.

5. The gateway system of claim 1 , wherein the first multiplexer is further connected to a first dispatch buffer controlled by the main processor.

6. The gateway system of claim 1 , wherein the second automatic dispatch module further comprises a plurality of second timers, and the second timers are configured to control the second dispatch registers to regularly output frames.

7. The gateway system of claim 1 , wherein the second multiplexer is further connected to a second dispatch buffer controlled by the main processor.

8. The gateway system of claim 1 , which is applied to a controller area network.

9. The gateway system of claim 1 , which is applied to a vehicle-based network system.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 2, 2019
From: SIEN INTEGRATION HOLDING LIMITED
To: INTEGRATED SILICON SOLUTION, INC.
Reel/Frame 048768/0010 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 19, 2019
From: VISION TECHNOLOGY VENTURES INC.
To: SIEN INTEGRATION HOLDING LIMITED
Reel/Frame 048374/0023 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2018
From: MYSON CENTURY, INC.
To: VISION TECHNOLOGY VENTURES INC.
Reel/Frame 046434/0551 →