Semiconductor device
View Patent ↗Double refresh executing means is changed in accordance with a manner (distributed refresh or burst refresh) of a refresh command so as to suppress a drop of internal power supply that occurs upon double refresh.
1. A semiconductor device comprising:
a refresh address unit producing refresh address information in response to issuance of a refresh command;
an address storage unit storing redundant address information accompanied with the refresh address information; and
a refresh control unit capable to perform a first refresh operation in which a refresh operation responsive to the refresh address information and a refresh operation responsive to the redundant address information are carried out in sequence prior to subsequent issuance of a refresh command.
2. The device as claimed in claim 1 , wherein the refresh control unit is further capable to perform a second refresh operation in which a refresh operation responsive to the refresh address information is carried out in parallel to a refresh operation responsive to the redundant address information, and the device further comprises a selection unit causing the refresh control unit to perform a selected one of the first and second refresh operations in response to the refresh command.
3. The device as claimed in claim 2 , wherein the refresh control unit is further capable to perform a third refresh operation in which a refresh operation responsive to the refresh address information and a refresh operation responsive to the redundant address information are carried out in response respectively to issuance of a refresh command and subsequent issuance of a refresh command, and the device further comprises a selection unit causing the refresh control unit to perform a selected one of the first, second and third refresh operations in response to the refresh command.
4. The device as claimed in claim 1 , wherein the refresh control unit is further capable to perform a fourth refresh operation in which a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.
5. The device as claimed in claim 2 , wherein the refresh control unit is further capable to perform a fourth refresh operation in which a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.
6. The device as claimed in claim 3 , wherein the refresh control unit is further capable to perform a fourth refresh operation in which a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.
7. A method of refreshing a semiconductor device comprising:
producing refresh address information in response to issuance of a refresh command;
storing redundant address information accompanied with the refresh address information; and
performing, when selected, a first refresh operation in which a refresh operation responsive to the refresh address information and a refresh operation responsive to the redundant address information are carried out in sequence prior to subsequent issuance of a refresh command.
8. The method as claimed in claim 7 , further comprising;
performing, when selected, a second refresh operation in which a refresh operation responsive to the refresh address information is carried out in parallel to a refresh operation responsive to the redundant address information.
9. The method as claimed in claim 8 , further comprising:
performing, when selected, a third refresh operation in which a refresh operation responsive to the refresh address information and a refresh operation responsive to the redundant address information are carried out in response respectively to issuance of a refresh command and subsequent issuance of a refresh command.
10. The method as claimed in claim 7 , further comprising:
performing a fourth refresh operation in which a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.
11. The method as claimed in claim 8 , further comprising:
performing a fourth refresh operation in which a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.
12. The method as claimed in claim 9 , further comprising:
performing a fourth refresh operation in which a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.
13. A semiconductor device comprising:
a memory cell array including a plurality of memory cells;
a refresh address unit producing refresh address information in response to issuance of a refresh command;
an address storage unit storing redundant address information accompanied with the refresh address information;
a refresh control unit capable to perform a first and a second refresh operation on the memory cell array, the first refresh operation being such that a refresh operation responsive to the refresh address information and a refresh operation responsive to the redundant address information are carried out in sequence prior to subsequent issuance of a refresh command, the second refresh operation being such that a refresh operation responsive to the refresh address information is carried out in parallel to a refresh operation responsive to the redundant address information; and
a selection unit causing the refresh control unit to perform a selected one of the first and second refresh operation in response to the refresh command.
14. The device as claimed in claim 13 , wherein the refresh control unit is further capable to perform a third refresh operation on the memory cell array, the third refresh operation being such that a refresh operation responsive to the refresh address information and a refresh operation responsive to the redundant address information are carried out in response respectively to issuance of a refresh command and subsequent issuance of a refresh command, and the selection unit further causes the refresh control unit to perform a selected one of the first, second and third refresh operations in response to the refresh command.
15. The device as claimed in claim 13 , wherein the refresh control unit is further capable to perform a fourth refresh operation on the memory cell array, the fourth refresh operation being such that a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.
16. The device as claimed in claim 14 , wherein the refresh control unit is further capable to perform a fourth refresh operation on the memory cell array, the fourth refresh operation being such that a refresh operation responsive to the refresh address information is carried out and a refresh operation responsive to the redundant address information is omitted when no redundant address information accompanied with the refresh address information is stored in the storage unit.