Reduction of gain switching induced phase jumps in high dynamic range downcoversion mixers

1. A system for minimizing phase jumps in an output signal, the system comprising:

an input module to receive an input voltage signal and convert the voltage signal to a current signal, the input module outputting the current signal;

a switching stage to receive the current signal and output a first signal comprising high-frequency upconverted products and low-frequency downconverted products;

an interface, comprising at least one capacitor, to receive the first signal and attenuate the high-frequency upconvereted products while outputting a second signal comprising the low-frequency downconverted products;

a load module to receive the second signal, the load module comprising an operational amplifier and at least one variable resistance load, with the load module outputting the output signal, a gain of the system determined by an impedance of the variable resistance load; and

wherein a product of a magnitude of the capacitor of the interface and a magnitude of the variable resistance load is substantially constant in view of varying the variable resistance load.

2. The system as recited in claim 1 , wherein a magnitude of the phase jumps is less than 2 degrees.

3. The system as recited in claim 1 , wherein the input voltage signal is received via a communications network, the network being selected form a group of networks comprising GSM, UMTS, and LTE (1.4 MHz, 3 MHz, 5 MHz, 10 MHz, 15 MHz, and 20 MHz).

4. The system as recited in claim 1 , wherein the load module further comprises a capacitance load, wherein the impedance is further defined as an impedance of the variable resistance load and the capacitance load.

5. The system as recited in claim 1 , wherein the input module comprises at least one transistor to convert the input voltage signal to the current signal.

6. The system as recited in claim 1 , wherein the switching stage comprises a plurality of transistors coupled between the input module and the interface, with a control terminal of each of the plurality of transistors being connected to a local oscillator source.

7. The system as recited in claim 1 , wherein the product of the magnitude of the capacitor and the magnitude of the variable resistance load has a tolerance of 50%.

8. A system for minimizing phase jumps in an output signal, the system comprising:

an input module to receive an input voltage signal and convert the voltage signal to a current signal, the input module outputting the current signal;

a switching stage to receive the current signal and output a first signal comprising high-frequency upconverted products and low-frequency downconverted products;

an interface, comprising at least one capacitor, to receive the first signal and attenuate the high-frequency upconvereted products while outputting a second signal comprising the low-frequency downconverted products, the interface further comprising an capacitance module comprising at least one additional capacitor;

a load module to receive the second signal, the load module comprising an operational amplifier and at least one variable resistance load, with the load module outputting the output signal, a gain of the system determined by an impedance of the variable resistance load; and

a digital control module communicatively coupled with the interface, with the digital control module selectively engaging the additional capacitors such that a product of a magnitude of a total capacitance at the interface and a magnitude of the variable resistance load is substantially constant in view of varying the variable resistance load.

9. The system as recited in claim 8 , wherein a magnitude of the phase jumps is less than 2 degrees.

10. The system as recited in claim 8 , wherein the input voltage signal is received via a communications network, the network being selected form a group of networks comprising GSM, UMTS, and LTE (1.4 MHz, 3 MHz, 5 MHz, 10 MHz, 15 MHz, and 20 MHz).

11. The system as recited in claim 8 , wherein the load module further comprises a capacitance load, wherein the impedance is further defined as an impedance of the variable resistance load and the capacitance load.

12. The system as recited in claim 8 , wherein the input module comprises at least one transistor to convert the input voltage signal to the current signal.

13. The system as recited in claim 8 , wherein the switching stage comprises a plurality of transistors coupled between the input module and the interface, with a control terminal of each of the plurality of transistors being connected to a local differential oscillator source.

14. The system as recited in claim 8 , wherein the product of the magnitude of the capacitor and the magnitude of the variable resistance load has a tolerance of 50%.

15. A method of minimizing phase jumps in an output signal, the method comprising:

receiving a input voltage signal and converting the voltage signal to a current signal;

mixing the current signal by a mixer to generate a first signal comprising high-frequency upconverted products and low-frequency downconverted products;

attenuating the high-frequency upconverted products by at least one capacitor to generate a second signal;

passing the second signal to a load, comprising an operational amplifier and at least one variable resistance load, with a gain of the input voltage signal determined by an impedance of the variable resistance load;

altering a magnitude of the resistance load; and

selectively engaging additional capacitors such that a product of a magnitude of a total capacitance between the mixer and the load and a magnitude of the variable resistance load is substantially constant in view of varying the variable resistance load.

16. The method as recited in claim 15 , wherein a magnitude of the phase jumps is less than 2 degrees.

17. The method as recited in claim 15 , wherein the input voltage signal is received via a communications network, the network being selected form a group of networks comprising GSM, UMTS, and LTE (1.4 MHz, 3 MHz, 5 MHz, 10 MHz, 15 MHz, and 20 MHz).

18. The method as recited in claim 15 , wherein the product of the magnitude of the capacitor and the magnitude of the variable resistance load has a tolerance of 50%.

19. The method as recited in claim 15 , wherein the load further comprises a capacitance load.

20. The method as recited in claim 15 , wherein converting further comprises at least one transistor converting the input voltage signal to the current signal.