IP Library Granted Patent US 7,795,971
Granted Patent B2
US 7,795,971 · App. 12/428,219 · Granted Sep 14, 2010

Electronic circuit and electronic device

Assignee: Seiko Epson Corporation
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Quick Facts
Patent No.
US 7,795,971
App. No.
12/428,219
Granted
Sep 14, 2010
Kind
B2
Abstract

An electronic circuit includes: a first amplifying circuit to which a first input signal is inputted; a second amplifying circuit to which a second input signal is inputted; a first drain ground amplifying transistor provided between a first power source node and an output node with control over the gate by the output from the first amplifying circuit; a second drain ground amplifying transistor provided between the first power source node and the output node with control over the gate by the output from the second amplifying circuit; a common load element provided between the output node and a second power source node; a first negative feedback path for negative feedback from the output node to the input of the first amplifying circuit; and a second negative feedback path for negative feedback from the output node to the input of the second amplifying circuit.

Claims (36)

1. An electronic circuit comprising:

a first amplifying circuit to which a first input signal is inputted;

a second amplifying circuit to which a second input signal is inputted;

a first drain ground amplifying transistor provided between a first power source node and an output node with control over the gate by the output from the first amplifying circuit;

a second drain ground amplifying transistor provided between the first power source node and the output node with control over the gate by the output from the second amplifying circuit;

a common load element provided between the output node and a second power source node;

a first negative feedback path for negative feedback from the output node to the input of the first amplifying circuit;

a second negative feedback path for negative feedback from the output node to the input of the second amplifying circuit; and

a combining circuit which combines an output signal from the first amplifying circuit and an output signal from the second amplifying circuit,

wherein the combining circuit outputs voltage corresponding to the voltage of the output signal from the amplifying circuit providing a smaller volume of feedback by the negative feedback control in the first and second amplifying circuits.

2. The electronic circuit according to claim 1 , wherein the combining circuit is an adding circuit for adding voltage of the output signal from the first amplifying circuit and voltage of the output signal from the second amplifying circuit.

3. The electronic circuit according to claim 1 , wherein the first amplifying circuit and the second amplifying circuit are differential amplifying circuits.

4. The electronic circuit according to claim 1 , wherein the first amplifying circuit and the second amplifying circuit are inverter circuits.

5. The electronic circuit according to claim 1 , wherein the first input signal and the second input signal are signals having equal signal level absolute values with respect to predetermined volume as reference and opposite signal level polarities with respect to predetermined voltage as reference.

6. An electronic circuit comprising:

a first amplifying circuit to which a first input signal is inputted;

a second amplifying circuit to which a second input signal is inputted;

a first drain ground amplifying transistor provided between a first power source node and an output node with control over the gate by the output from the first amplifying circuit;

a second drain ground amplifying transistor provided between the first power source node and the output node with control over the gate by the output from the second amplifying circuit;

a common load element provided between the output node and a second power source node;

a first negative feedback path for negative feedback from the output node to the input of the first amplifying circuit;

a second negative feedback path for negative feedback from the output node to the input of the second amplifying circuit; and

a clamp circuit which limits amplitudes of the respective output signals from the first amplifying circuit and the second amplifying circuit.

7. The electronic circuit according to claim 1 , wherein the negative feedback control is performed via non-linear elements provided on the first negative feedback path and the second negative feedback path.

8. An electronic device comprising:

a low-noise amplifying circuit to which a receiving signal is inputted;

an absolute value detecting circuit as an electronic circuit to which a first input signal and a second input signal having an output signal of the low-noise amplifying circuit are inputted;

a low pass filter to which an output from the absolute value detecting circuit is inputted; and

a signal processing unit to which an output from the low pass filter is inputted, the electronic circuit comprising:

a first amplifying circuit to which the first input signal is inputted;

a second amplifying circuit to which the second input signal is inputted;

a first drain ground amplifying transistor provided between a first power source node and an output node with control over the gate by the output from the first amplifying circuit;

a second drain ground amplifying transistor provided between the first power source node and the output node with control over the gate by the output from the second amplifying circuit;

a common load element provided between the output node and a second power source node;

a first negative feedback path for negative feedback from the output node to the input of the first amplifying circuit; and

a second negative feedback path for negative feedback from the output node to the input of the second amplifying circuit.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 28, 2019
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 050197/0212 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 22, 2009
From: IKEDA, MASAYUKI
To: SEIKO EPSON CORPORATION
Reel/Frame 022581/0531 →
Priority Claims (2)
JP 2008-121929 · May 8, 2008 · national
JP 2009-066742 · Mar 18, 2009 · national
Continuity (1)
Related Publication 20090278600A1 · Nov 12, 2009