IP Library Granted Patent US 7,876,158
Granted Patent B2
US 7,876,158 · App. 12/429,956 · Granted Jan 25, 2011

High gain stacked cascade amplifier with current compensation to reduce gain compression

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Quick Facts
Patent No.
US 7,876,158
App. No.
12/429,956
Granted
Jan 25, 2011
Kind
B2
Abstract

A high gain stacked cascade amplifier includes a first amplifying element, a second amplifying element, a current mirror bias element, and a dynamic bias adjustment element. The first and second amplifying elements are coupled in series to form the high gain stacked cascade amplifier configuration. The current mirror bias element provides a bias to the first and second amplifying elements. The dynamic bias adjustment element is coupled to the second amplifying element. The dynamic bias adjustment element is configured to increase a gain compression point of a composite filter, formed by the first and second amplifying elements, in response to a determination that an input signal causes gain compression in the first amplifying element.

Claims (18)

1. A high gain stacked cascade amplifier comprising:

a first amplifying element;

a second amplifying element coupled in series with the first amplifying element within a high gain stacked cascade amplifier configuration, wherein an output of the first amplifying element is coupled to an input of the second amplifying element;

a current mirror bias element coupled to the first and second amplifying elements, wherein the current mirror bias element is configured to bias the first and second amplifying elements; and

a dynamic bias adjustment element coupled to the second amplifying element, the dynamic bias adjustment element configured to increase a gain compression point of a composite filter, formed by, the first and second amplifying elements, in response to a determination that an input signal of the first amplifying element causes gain compression in the first amplifying element.

2. The high gain stacked cascade amplifier of claim 1 , further comprising a capacitor coupled between the output of the first amplifying element and the input of the second amplifying element, wherein the capacitor is configured to convey an amplified signal from the output of the first amplifying element to the input of the second amplifying element.

3. The high gain stacked cascade amplifier of claim 1 , further comprising a bypass capacitor coupled to a source of the second amplifying element, the bypass capacitor to ground the source of the second amplifying element.

4. The high gain stacked cascade amplifier of claim 1 , wherein the second amplifying element comprises an impedance load, wherein the impedance load comprises a resistor.

5. The high gain stacked cascade amplifier of claim 1 , wherein the second amplifying element comprises an impedance load, wherein the impedance load comprises an inductor.

6. The high gain stacked cascade amplifier of claim 1 , wherein the first and second amplifying elements comprise CMOS enhancement-mode transistors.

7. The high gain stacked cascade amplifier of claim 1 , wherein the first and second amplifying elements comprise GaAs enhancement-mode transistors.

8. A method of manufacturing a high gain stacked cascade amplifier, the method comprising:

coupling first and second amplifying elements in a high gain stacked cascade amplifier configuration;

coupling a current mirror bias element to the first and second amplifying elements to bias the first and second amplifying elements;

coupling a dynamic bias adjustment element to the second amplifying element to increase a gain compression point of a composite amplifier, formed by the first and second amplifying elements, in response to a determination that an input signal of the first amplifying element causes gain compression in the first amplifying element; and

coupling an output of the first amplifying element to an input of the dynamic bias adjustment element.

9. The method of claim 8 , further comprising coupling a source of the dynamic bias adjustment element between two resistors of a bias resistance to bias the first amplifying element.

10. The method of claim 8 , further comprising coupling a capacitor to an input of the first amplifying element, wherein the capacitor is configured to convey an input signal to the input of the first amplifying element.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE PROPERTY NUMBERS PREVIOUSLY RECORDED AT REEL: 47630 FRAME: 344. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Mar 21, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0267 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE OF MERGER TO 9/5/2018 PREVIOUSLY RECORDED AT REEL: 047196 FRAME: 0687. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047630/0344 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047196/0687 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
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PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032851-0001) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 037689/0001 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032851/0001 →
MERGER Recorded May 7, 2013
From: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 030369/0703 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 24, 2009
From: CHOW, YUT HOONG; TAN, HIANG TEIK
To: AVAGO TECHNOLOGIES WIRELESS IP (SINGAPORE) PTE. LTD.
Reel/Frame 022603/0392 →