Complex-admittance digital-to-analog converter

1. A circuit including a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference voltage signal and (2) as a function of a digital input signal, said converter comprising:

at least one reference terminal configured to receive the reference voltage signal;

an output terminal configured to provide the analog output signal as a function of the digital input signal;

a plurality of non-trivially complex admittances, each of a known and finite value; and

a plurality of switches responsive to the digital input signal and configured to selectively couple the non-trivially complex admittances between the reference terminal or terminals and the output terminal.

2. The circuit of claim 1 , wherein the non-trivially complex admittances are substantially scalar multiples of a master admittance.

3. The circuit of claim 2 , wherein the on-state admittances of the switches are scaled by similar multiples as those of the corresponding non-trivially complex admittances, so as to reduce or eliminate the accuracy degradation due to the admittance of each switch.

4. The circuit of claim 2 , further including at least one reference circuit coupled and presenting an admittance to the reference terminal, the admittance of the reference circuit being such that when coupled to the non-trivially complex admittances the accuracy degradation due to the admittance of the reference circuit is reduced or eliminated.

5. The circuit of claim 4 , further including a plurality of reference terminals, wherein the admittance presented at each reference terminal is such that when coupled to anon-trivially complex admittance the accuracy degradation due to the input admittance provided each reference terminal is reduced or eliminated.

6. The circuit of claim 1 , wherein the circuit comprises an analog-to-digital converter, the analog-to-digital converter including the digital-to-analog converter.

7. The circuit of claim 6 , wherein an admittance separate from the digital to analog converter is used to sample the input signal.

8. The circuit of claim 6 , wherein the analog-to-digital converter is configured to provide analog-to-digital conversion at least partially by successive approximation.

9. The circuit of claim 8 , wherein the analog-to-digital converter is configured to provide error correction as a part of successive approximation.

10. The circuit of claim 8 , wherein the plurality of non-trivially complex admittances have a split bit weight structure.

11. The circuit of claim 1 , wherein the circuit includes a differential circuit including a second digital-to-analog converter having a second output terminal, the second digital-to-analog converter producing an output signal at the second output terminal also representative of the same digital input signal, wherein the two output terminals provide a substantially differential output signal.

12. The circuit of claim 1 , further including a second digital-to-analog converter configured to operate with the first mentioned digital-to-analog converter as a compound digital to analog converter, said second digital-to-analog converter comprising:

an output terminal coupled to the output terminal of the first mentioned digital-to-analog converter for providing an output analog signal indicative of a second digital input signal.

13. A circuit including a digital-to-analog converter configured to produce an analog output signal (1) proportional to a reference voltage signal and (2) as a function of a digital input signal, said converter comprising:

a plurality of non-trivially complex admittances, each of a known and finite value, and configured so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference voltage signal and an output terminal.

14. The circuit of claim 13 , wherein the non-trivially complex admittances are substantially scalar multiples of a master admittance.

15. The circuit of claim 13 , wherein the circuit comprises an analog-to-digital converter, the analog-to-digital converter including the digital-to-analog converter.

16. The circuit of claim 15 , wherein an admittance separate from the digital to analog converter is used to sample the input signal.

17. The circuit of claim 15 , wherein the analog-to-digital converter is configured to provide analog-to-digital conversion at least partially by successive approximation.

18. The circuit of claim 17 , wherein the analog-to-digital converter is configured to provide error correction as a part of successive approximation.

19. The circuit of claim 13 , wherein each non-trivially complex admittance includes at least one resistor and at least one susceptance element.

20. The circuit of claim 19 , wherein the at least one susceptance element is a capacitor.

21. The circuit of claim 19 , wherein the at least one susceptance element is an inductor.

22. A method of converting a digital signal to an analog signal, the method comprising:

selectively switching non-trivially complex admittances, each of a known and finite value, as a function of the digital signal between a reference voltage terminal and an output terminal.

23. A method according to claim 22 , wherein selectively switching each of a plurality of non-trivially complex admittance values includes selectively switching non-trivially complex admittances in a predetermined sequence.

24. A method according to claim 23 , wherein the digital signal includes a plurality of binary bits capable of being presented as either a binary state one or binary state zero, and the values of the non-trivial complex admittances vary so as to correspond to all of the potential binary values of the bits of digital signal, and wherein selectively switching non-trivially complex admittances includes selectively switching only those non-trivial complex admittances corresponding to those bits that presented as a binary state of one.

25. A method of converting a digital input signal to an analog output signal, the method comprising

receiving at least one reference voltage signal at a corresponding reference terminal;

providing the analog output signal at an output terminal as a function of the digital input signal;

controlling a plurality of switches responsively to the digital input signal so as to selectively couple non-trivially complex admittances, each of a known and finite value, between the reference terminal or terminals and the output terminal so that the analog output signal is (1) proportional to a reference voltage signal and (2) a function of a digital input signal.

26. The method of claim 25 , further including arranging the non-trivially complex admittances so that they are substantially scalar multiples of a master admittance.

27. The method of claim 26 , further including arranging the on-state admittances of the switches so that they are scaled by similar multiples as those of the corresponding non-trivially complex admittances, so as to reduce or eliminate the accuracy degradation due to the admittance of each switch.

28. The method of claim 26 , further presenting an admittance of a reference circuit to the reference terminal such that when coupled to the non-trivially complex admittances the accuracy degradation due to the admittance of the reference circuit is reduced or eliminated.

29. The method of claim 28 , further including coupling the admittances to a plurality of reference terminals so that the admittance presented at each reference terminal is such that when coupled to a non-trivially complex admittance the accuracy degradation due to the input admittance provided each reference terminal is reduced or eliminated.

30. The method of claim 25 , wherein converting a digital input signal to an analog output signal is performed within an analog-to-digital converter.

31. The method of claim 30 , wherein an admittance separate from the non-trivially complex admittances is used to sample the input signal.

32. The method of claim 30 , further including converting an analog signal to a digital signal within the analog to digital converter at least partially in accordance with successive approximation.

33. The method of claim 32 , further including providing error correction as a part of successive approximation.

34. The method of claim 32 , further including arranging the plurality of non-trivially complex admittances so that they have a split bit weight structure.

35. The method of claim 25 , further including providing two analog output signals at two respective output terminals so as to provide a substantially differential output signal.

36. The method of claim 25 , further including providing two digital-to-analog converters, at least one of the converters including non-trivially complex admittances, and configured to operate as a compound digital to analog converter.

37. A method of producing an analog output signal (1) proportional to a reference voltage signal and (2) as a function of a digital input signal, comprising:

configuring a plurality of non-trivially complex admittances, each of a known and finite value, so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference voltage signal and an output terminal.

38. The method of claim 37 , wherein configuring the non-trivially complex admittances includes configuring the non-trivially complex admittances so that they are substantially scalar multiples of a master admittance.

39. The method of claim 37 , wherein producing an analog signal is performed within an analog-to-digital converter.

40. The method of claim 37 , further including sampling the input signal with an admittance separate from the plurality of non-trivially complex admittances.

41. The method of claim 39 , wherein configuring a plurality of non-trivially complex admittances so that each non-trivially complex admittance can be selectively switched as a function of the digital input signal so as to be coupled between a reference terminal configured to receive a reference voltage signal and an output terminal, wherein the switching is performed at least partially by successive approximation.

42. The method of claim 41 , wherein switching includes error correction as a part of successive approximation.

43. The method of claim 37 , further including configuring each non-trivially complex admittance so that it includes at least one resistor and at least one susceptance element.

44. The method of claim 43 , further including configuring each non-trivially complex admittance so that it includes at least one resistor and at least one capacitor.

45. The method of claim 43 , further including configuring each non-trivially complex admittance so that it includes at least one resistor and at least one inductor.