Device and method for generating an output signal

1. A device for generating an output signal as a function of an input signal, comprising:

an input,

at least two circuit sections, wherein each circuit section of the at least two circuit sections is configured for generating a partial output signal,

wherein the at least two circuit sections are coupled to the input in such a way that each of the at least two circuit sections has applied to it an input signal applied to the input plus an offset assigned to each circuit section, wherein at least two of the at least two circuit sections are assigned a different offset, and

a further circuit section for combining the partial output signals of the at least two circuit sections to form an output signal,

wherein each of the circuit sections determines a part of a ramped characteristic curve of the device.

2. The device as claimed in claim 1 , wherein one of the at least two circuit sections is assigned an offset of zero.

3. The device as claimed in claim 1 , wherein each of the at least two circuit sections comprises an amplifier.

4. The device as claimed in claim 3 , wherein the amplifier comprises a differential amplifier, and wherein each differential amplifier is assigned a current source.

5. The device as claimed in claim 4 , wherein the current sources are adjustable.

6. The device as claimed in claim 4 , wherein each differential amplifier comprises a first transistor and a second transistor, wherein a control input of the first transistors is coupled to the input in such a way that they have applied to them the input signal applied to the input plus the respective offset, and wherein control inputs of the respective second transistors are coupled to a voltage source.

7. The device as claimed in claim 4 , wherein each differential amplifier comprises a first transistor and a second transistor, wherein a control input of the first transistors is coupled to the input in such a way that they have applied to them the input signal applied to the input plus the respective offset, and wherein control inputs of the respective second transistors are coupled to a further input.

8. The device as claimed in claim 1 , wherein the respective offsets are independent from said input signal.

9. The device as claimed in claim 1 , wherein the device is manufactured using CMOS technology.

10. The device as claimed in claim 1 , comprising a circuit section for generating a further partial output signal, wherein the device is configured in such a way that the further partial output signal is subtracted from at least one of the partial output signals.

11. A signal generating device for generating a plurality of output signals, comprising:

a plurality of devices for generating a respective output signal as a function of a respective input signal, each device comprising:

an input,

at least two circuit sections, wherein each circuit section of the at least two circuit sections is configured for generating a partial output signal,

wherein the at least two circuit sections are coupled to the input in such a way that each of the at least two circuit sections has applied to it an input signal applied to the input plus an offset assigned to each circuit section, wherein at least two of the at least two circuit sections are assigned a different offset, and

a further circuit section for combining the partial output signals of the at least two circuit sections to form said respective output signal,

wherein the devices have at least one common input, and

wherein each of the devices has a ramped characteristic curve.

12. The signal generating device as claimed in claim 11 , wherein the offsets assigned to the circuit sections of the devices differ at least partly from device to device.

13. The signal generating device as claimed in claim 11 , wherein each of the devices has a circuit section which is assigned an offset which corresponds to an offset assigned to a circuit section of another device.

14. An amplifier arrangement, comprising:

an amplifier input,

an amplifier output,

a plurality of parallel amplifier stages, wherein each of the amplifier stages is coupled to the amplifier input and an output of each of the amplifier stages is coupled to the amplifier output, and

a signal generating device, wherein the signal generating device is configured for generating a number of output signals corresponding to a number of amplifier stages and wherein a respective output of the signal generating device is coupled to a respectively assigned amplifier stage of the amplifier stages in such a way that a gain of the respective amplifier stage is adjustable by means of the respective output signal of the signal generating device, the signal generating device comprising:

a plurality of devices for generating a respective output signal as a function of a respective input signal, each device comprising:

an input,

at least two circuit sections, wherein each circuit section of the at least two circuit sections is configured for generating a partial output signal,

wherein the at least two circuit sections are coupled to the input in such a way that each of the at least two circuit sections has applied to it an input signal applied to the input plus an offset assigned to each circuit section,

wherein at least two of the at least two circuit sections are assigned a different offset, and

a further circuit section for combining the partial output signals of the at least two circuit sections to form said respective output signal,

wherein the devices have at least one common input.

15. The amplifier arrangement as claimed in claim 14 , wherein each of the amplifier stages comprises a differential amplifier, wherein the output of the device assigned to the respective amplifier stage is coupled to a current input of the differential amplifier of the amplifier stage.

16. The amplifier arrangement as claimed in claim 15 , wherein each of the differential amplifiers comprises a first transistor and a second transistor, wherein, in each differential amplifier, a dimensioning of the first transistor is identical to a dimensioning of the second transistor, and wherein the transistors of a first differential amplifier of the differential amplifiers are dimensioned differently than the transistors of a second differential amplifier of the differential amplifiers.

17. The amplifier device as claimed in claim 16 , wherein the different dimensioning comprises different gate widths.

18. The amplifier device as claimed in claim 14 , wherein each amplifier stage comprises a cascode circuit having a first transistor and a second transistor wherein a control input of each first transistor is coupled to the amplifier input, and wherein a control input of each second transistor is coupled to the respectively assigned output of the signal generating device.

19. The amplifier device as claimed in claim 18 , wherein each of the second transistors is coupled to the respective device via at least one element selected from the group comprising a replica bias arrangement and a current/voltage converter.

20. A method for amplifying a signal, comprising:

generating a plurality of control signals in accordance with a plurality of offset ramped characteristic curves as a function of a control input signal,

leading each control signal of the plurality of control signals to a respectively assigned amplifier stage for setting a gain of the respective amplifier stage, and

amplifying an input signal by means of the plurality of amplifier stages.

21. The method as claimed in claim 20 , wherein the step of generating a plurality of control signals comprises:

generating a plurality of partial control signals for each control signal, wherein each partial control signal determines a part of the respective ramped characteristic curve, and composing the plurality of control signals from the partial control signals.

22. The method as claimed in claim 21 , comprising:

generating a further partial control signal, and

subtracting the further partial control signal from at least one of the partial control signals.