Analog iterative decoder with early-termination
View Patent ↗An iterative decoder comprising a transconductance amplifier, a sampler, a Min-Sum decoder, and an early determination module is provided. The transconductance amplifier outputs a current proportional to the voltage of the coded bit stream. The sampler converts the amplified current into a plurality of currents and stores the sampled currents in a plurality of buffers. The Min-Sum decoder receives parallel currents, wherein currents represent the message of each variable node. The Min-Sum decoder exchanges the message of variable nodes and check nodes iteratively and outputs a set of decode codewords according to the possibilities. The early terminating module stops the iterative decoding when the decoded codeword converged.
1. A decoder, comprising:
the coded bit stream;
a serial-to-parallel sampler that receives, from a transconductance amplifier, an amplified current proportional to a voltage of a coded bit stream and converts the amplified current into a plurality of sampled currents and stores the plurality of sampled currents in a plurality of buffers;
an analog min-sum decoder that receives the plurality of sampled currents from the plurality of buffers, wherein the plurality of sampled currents represent respective possibilities of a bit being 0 or 1, performs iterative decoding including iterative exchanges of the respective possibilities across a plurality of variable nodes and check nodes, and outputs a set of decoded codewords according to the respective possibilities; and
an early terminating module that stops the iterative decoding in the analog min-sum decoder in response to convergence of the decoded codeword.
2. The decoder of claim 1 , wherein the transconductance amplifier is a rail-to-rail transconductance amplifier with a range of an input or output voltage operating from a positive power supply to a negative power supply.
3. The decoder of claim 1 , wherein the early terminating module stops the iterative decoding in the analog min-sum decoder in response to performance of a pre-determined number of iterations.
4. The decoder of claim 1 , wherein the early terminating module stops the iterative decoding in the analog min-sum decoder in response to attainment of a pre-determined performance threshold.
5. The decoder of claim 1 , wherein the early termination module is a cyclic redundancy check (CRC) control circuit module that stops the iterative decoding in the analog min-sum decoder in response to the decoded codeword having passed a CRC check.
6. The decoder of claim 1 , wherein the analog min-sum decoder further comprises:
a variable-node module that calculates a plurality of variable nodes messages M v→c according to an equation
M
v
→
c
=
∑
i
∈
N
(
C
)
\
C
M
i
→
v
+
M
v
(
0
)
,
wherein
M
v
(
0
)
is an initial input at a variable node v and N(C)\C represents a first set of neighboring nodes; and
a check-node module that calculates a plurality of check nodes messages M c→v according to an equation
M
c
→
v
=
∏
i
∈
N
(
C
)
\
V
sgn
(
M
i
→
c
)
·
min
i
∈
N
(
C
)
\
v
M
i
→
c
,
where N(C)\V represents a second set of neighboring nodes, and sgn(.) returns 1 or −1 depending on a corresponding argument being non-negative or negative, respectively.
7. The decoder of claim 6 , wherein the analog min-sum decoder further comprises an analog switch coupled with the variable-node module and the check-node module, and the analog switch terminates a connection between the variable-node module and the check-node module in response to the early termination module having signaled a stop sign.
8. The decoder of claim 7 , wherein the analog min-sum decoder further comprises a 2:1 analog multiplexer that selects the initial input and a minimum current as inputs to the variable-node module, and in response to the early termination module having signaled the stop sign, the analog min-sum chooses the minimum current as the input to the variable-node module.
9. The decoder of claim 1 , wherein the early termination module is an analog circuit.
10. The decoder of claim 6 , wherein the check-node module further comprises:
a real to absolute sign module that extracts signs and magnitudes of incoming messages received from other variable nodes that are connected to a check node;
a set of minimum winner-take-all (WTA) modules that find respective minimum values among the magnitudes of the incoming messages from the other variable nodes;
a set of sign multipliers that multiply respective signs of the incoming messages received from the other variable nodes; and
a set of absolute value and sign to real converters that combine sign bits and absolute values and to generate outgoing messages as a function of the incoming messages.
11. The decoder of claim 9 , wherein the set of sign multipliers are implemented with at least one XOR logic gate.
12. A method comprising:
receiving, by a device including at least one processor from a transconductance amplifier, an amplified current proportional to a voltage of a coded bit stream;
converting the amplified current into a plurality of sampled currents;
storing the plurality of sampled currents in a plurality of buffers;
iteratively exchanging a plurality of possibilities of bits to be 0 or 1 across a plurality of variable nodes and a plurality of check nodes, wherein the plurality of possibilities are represented as currents;
outputting a set of decode codewords according to the plurality of possibilities; and
stopping the iteratively exchanging in response to one of the decoded codewords converging.
13. The method of claim 12 further comprising, stopping the iteratively exchanging in response to reaching a pre-determined performance threshold.
14. The method of claim 12 further comprising, stopping the iteratively exchanging in response to a decoded codeword passing a cyclic redundancy check control check.
15. The method of claim 12 , wherein the iteratively exchanging the plurality of possibilities further comprises:
determining a plurality of variable node messages M v→c according to an equation
M
v
→
c
=
∑
i
∈
N
(
C
)
\
C
M
i
→
v
+
M
v
(
0
)
,
wherein
M
v
(
0
)
is an initial input at a variable node v and N(C)\C represents a first set of neighboring nodes; and
determining a plurality of check node messages M c→v according to an equation
M
c
→
v
=
∏
i
∈
N
(
C
)
\
V
sgn
(
M
i
→
c
)
·
min
i
∈
N
(
C
)
\
v
M
i
→
c
,
where N(C)\V represents a second set of neighboring nodes, and sgn(.) returns 1 or −1 based at least in part upon an argument of sgn(.) being non-negative or negative, respectively.
16. A system comprising:
means for receiving an amplified current proportional to a voltage of a coded bit stream from a transconductance amplifier;
means for converting the amplified current into a plurality of sampled currents;
means for iteratively exchanging a plurality of possibilities of bits across a plurality of variable nodes and a plurality of check nodes, wherein the plurality of possibilities are represented as a plurality of currents;
means for outputting a set of decoded codewords according to the plurality of possibilities; and
means for ceasing operation of the means for iteratively exchanging in response to one of the decoded codewords converging.
17. The system of claim 16 further comprising:
means for ending operation of the means for iteratively exchanging in response to attaining a pre-determined performance threshold.
18. The system of claim 16 further comprising, means for ending operation of the means for iteratively exchanging in response to a decoded codeword passing a cyclic redundancy check control check.
19. The system of claim 16 , wherein the means for iteratively exchanging the plurality of possibilities further comprises:
means for calculating a plurality of variable node messages M v→c according to an equation
M
v
→
c
=
∑
i
∈
N
(
C
)
\
C
M
i
→
v
+
M
v
(
0
)
,
wherein
M
v
(
0
)
is an initial input at a variable node v and N(C)\C represents a first set of neighboring nodes; and
means for calculating a plurality of check nodes messages M c→v according to an equation
M
c
→
v
=
∏
i
∈
N
(
C
)
\
V
sgn
(
M
i
→
c
)
·
min
i
∈
N
(
C
)
\
v
M
i
→
c
,
where N(C)\V represents a second set of neighboring nodes, and sgn(.) returns 1 or −1 based at least in part upon an argument of sgn(.) being non-negative or negative, respectively.
20. The system of claim 16 , further comprising:
means for storing the plurality of sampled currents in a plurality of buffers.
21. A non-transitory computer-readable storage medium comprising computer-readable instructions that, in response to execution, cause a computing system including at least one processor to perform operations, comprising:
receiving an amplified current proportional to a voltage of a coded bit stream from a transconductance amplifier;
converting the amplified current into a plurality of sampled currents;
storing the plurality of sampled currents in a plurality of buffers;
iteratively exchanging a plurality of possibilities of bits to be 0 or 1 across a plurality of variable nodes and a plurality of check nodes, wherein the plurality of possibilities are represented as currents;
outputting a set of decode codewords according to the plurality of possibilities; and
stopping the iteratively exchanging in response to one of the decoded codewords converging.
22. The computer-readable storage medium of claim 21 , the operations further comprising:
stopping the iteratively exchanging in response to reaching a pre-determined performance threshold.
23. The computer-readable storage medium of claim 21 , the operations further comprising:
stopping the iteratively exchanging in response to a decoded codeword passing a cyclic redundancy check control check.
24. The computer-readable storage medium of claim 21 , wherein the iteratively exchanging the plurality of possibilities further comprises:
determining a plurality of variable node messages M v→c according to an equation
M
v
→
c
=
∑
i
∈
N
(
C
)
\
C
M
i
→
v
+
M
v
(
0
)
,
wherein
M
v
(
0
)
is an initial input at a variable node v and N(C)\C represents a first set of neighboring nodes; and
determining a plurality of check node messages M c→v according to an equation
M
c
→
v
=
∏
i
∈
N
(
C
)
\
V
sgn
(
M
i
→
c
)
·
min
i
∈
N
(
C
)
\
v
M
i
→
c
,
where N(C)\V represents a second set of neighboring nodes, and sgn(.) returns 1 or −1 based at least in part upon an argument of sgn(.) being non-negative or negative, respectively.