Method of manufacturing semiconductor integrated circuit device with high and low breakdown-voltage MISFETs
View Patent ↗Provided is a manufacturing method of a semiconductor integrated circuit device having a plurality of first MISFETs in a first region and a plurality of second MISFETs in a second region, which comprises forming a first insulating film between two adjacent regions of the first MISFET forming regions in the first region and the second MISFET forming regions in the second region; forming a second insulating film over the surface of the semiconductor substrate between the first insulating films in each of the first and second regions; depositing a third insulating film over the second insulating film; forming a first conductive film over the third insulating film in the second region; forming, after removal of the third and second insulating films from the first region, a fourth insulating film over the surface of the semiconductor substrate in the first region; and forming a second conductive film over the fourth insulating film; wherein the third insulating film remains over the first insulating film in the second region. The present invention makes it possible to raise the threshold voltage of a parasitic MOS and in addition, to suppress occurrence of an NBT phenomenon.
1. A method of manufacturing a semiconductor integrated circuit device having a first MISFET in a first MISFET forming region of a semiconductor substrate, comprising steps of:
(a) forming grooves in the first MISFET forming region of the semiconductor substrate;
(b) depositing a first insulating film over the first MISFET forming region of the semiconductor substrate;
(c) polishing the first insulating film in order to embed the first insulating film into the grooves;
(d) forming first semiconductor regions in the first MISFET forming region of the semiconductor substrate, wherein the first semiconductor regions serve as part of source and drain regions of the first MISFET;
(e) forming a first gate insulating film of the first MISFET over the first MISFET forming region of the semiconductor substrate by a thermal oxidation method;
(f) forming a second gate insulating film of the first MISFET over the first gate insulating film and the first insulating film by a CVD method;
(g) forming a first gate electrode of the first MISFET over the second gate insulating film; and
(h) forming second semiconductor regions in the first MISFET forming region of the semiconductor substrate, wherein the second semiconductor regions serve as part of source and drain regions of the first MISFET,
wherein the first MISFET is used for a driver of a liquid crystal display,
wherein an impurity concentration of the second semiconductor regions is higher than an impurity concentration of the first semiconductor regions,
wherein the first semiconductor regions surround the second semiconductor regions and the grooves,
wherein a thickness of the second gate insulating film is thicker than a thickness of the first gate insulating film,
wherein ends of the second gate insulating film are formed over the first insulating film in a direction from the source region to the drain region, and
wherein ends of the first gate electrode are formed over the first insulating film through the second insulating film in a direction from the source region to the drain region.
2. A method of manufacturing a semiconductor integrated circuit device according to claim 1 ,
wherein the first and second semiconductor regions are formed of n-type impurities.
3. A method of manufacturing a semiconductor integrated circuit device according to claim 1 ,
wherein the first and second semiconductor regions are formed of p-type impurities.
4. A method of manufacturing a semiconductor integrated circuit device having a first MISFET in a first MISFET forming region of a semiconductor substrate, comprising steps of:
(a) forming grooves in the first MISFET forming region of the semiconductor substrate;
(b) depositing a first insulating film over the first MISFET forming region of the semiconductor substrate;
(c) polishing the first insulating film in order to embed the first insulating film into the grooves;
(d) forming first semiconductor regions in the first MISFET forming region of the semiconductor substrate, wherein the first semiconductor regions serve as part of source and drain regions of the first MISFET;
(e) forming a first gate insulating film of the first MISFET over the first MISFET forming region of the semiconductor substrate by a thermal oxidation method;
(f) forming a second gate insulating film of the first MISFET over the first gate insulating film and the first insulating film by a CVD method;
(g) forming a first gate electrode of the first MISFET over the second gate insulating film; and
(h) forming second semiconductor regions in the first MISFET forming region of the semiconductor substrate, wherein the second semiconductor regions serve as part of source and drain regions of the first MISFET,
wherein the first MISFET is used for a driver of a liquid crystal display,
wherein an impurity concentration of the second semiconductor regions is higher than an impurity concentration of the first semiconductor regions,
wherein the first semiconductor regions surround the second semiconductor regions and the grooves,
wherein a thickness of the second gate insulating film is thicker than a thickness of the first gate insulating film,
wherein ends of the second gate insulating film are formed over the first insulating film in a direction from the source region to the drain region,
wherein ends of the first gate electrode are formed over the first insulating film through the second insulating film in a direction from the source region to the drain region,
wherein the first insulating film, the first gate insulating film and the second gate insulating film are formed of a silicon oxide film, and
wherein the gate electrode is formed of a poly silicon film and a silicide film formed on the poly silicon film.
5. A method of manufacturing a semiconductor integrated circuit device according to claim 4 ,
wherein the first and second semiconductor regions are formed of n-type impurities.
6. A method of manufacturing a semiconductor integrated circuit device according to claim 4 ,
wherein the first and second semiconductor regions are formed of p-type impurities.