Thin film transistor array panel and method of manufacturing the same
View Patent ↗A method of manufacturing a thin film transistor array panel is provided, which includes: forming a semiconductor layer of polysilicon on an insulating substrate; forming a gate insulating layer on the semiconductor layer; forming a gate electrode on the gate insulating layer; forming a source region and a drain region by doping conductive impurities in the semiconductor layer; forming an interlayer insulating layer covering the gate electrode; forming a source electrode and a drain electrode respectively connected to the source and the drain regions; forming a passivation layer covering the source and the drain electrodes; forming a pixel electrode connected to the drain electrode; and forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode, wherein one selected from the semiconductor layer, the gate electrode, the source and the drain electrodes, and the pixel electrode is at least formed by photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.
1. A method of manufacturing a thin film transistor array panel, comprising:
forming a semiconductor layer of polysilicon on an insulating substrate;
forming a gate insulating layer on the semiconductor layer;
forming a gate electrode on the gate insulating layer;
forming a source region and a drain region by doping conductive impurities in the semiconductor layer;
forming an interlayer insulating layer covering the gate electrode;
forming a source electrode and a drain electrode respectively connected to the source and the drain regions;
forming a passivation layer covering the source and the drain electrodes;
forming a pixel electrode connected to the drain electrode; and
forming a first alignment key when forming one selected from the semiconductor layer, the gate electrode, the source electrode, the drain electrode, and the pixel electrode,
wherein one selected from the semiconductor layer, the gate electrode, the source electrode, the drain electrode, and the pixel electrode is at least formed by a photolithography process using a photoresist pattern as an etch mask, and a second alignment key completely covering the first alignment key is formed at the same layer as the photoresist pattern.
2. The method of claim 1 wherein the first alignment key includes a display portion representing the shape of the first alignment key, a detection portion defining the outline of the first alignment key, and a circumferential portion disposed between the display portion and the detection portion.
3. The method of claim 2 , wherein the detection portion is in relief.
4. The method of claim 2 , wherein the detection portion is in intaglio.
5. The method of claim 1 , wherein the thin film transistor array panel is a display panel for a liquid crystal display.
6. The method of claim 1 , wherein the thin film transistor array panel is a display panel for an organic light emitting display.