Method for fabricating a flat panel display
View Patent ↗The method for fabricating a flat panel display includes performing a first crystallization process to re-crystallize an amorphous silicon layer on a glass substrate to make the amorphous silicon layer become a polysilicon layer, forming a patterned absorbing layer to cover an active area pattern of a driving TFT and to expose portions of the polysilicon layer, performing a second crystallization process to re-crystallization the exposed portions of the polysilicon layer so that the exposed portions of the polysilicon layer has a different grain structure from the grain structure of the driving TFT, removing the patterned absorbing layer, and removing portions of the polysilicon layer to form an active area of the driving TFT and an active area of a switching TFT area in the exposed portions of the polysilicon layer of each sub-pixel.
1. A method for fabricating a flat panel display, the flat panel display comprising a plurality of sub-pixels and a periphery circuit area, the method comprising:
providing a substrate;
forming an amorphous silicon layer on the substrate;
performing a first crystallization process to crystallize the amorphous silicon layer so that the amorphous silicon layer becomes a polysilicon layer;
forming a patterned absorbing layer to cover an active area pattern of a driving thin film transistor (TFT) in each of the sub-pixels and to expose portions of the polysilicon layer;
performing a second crystallization process to re-crystallize the exposed portions of the polysilicon layer so that a grain structure of the exposed portions of the polysilicon layer is different from a grain structure of a plurality of active areas covered by the active area patterns of the driving TFTs;
removing the patterned absorbing layer; and
removing portions of the polysilicon layer to form the active area of the driving TFT and to form an active area of a switching TFT in the exposed portions of the polysilicon layer of each sub-pixel, and to form at least an active area of a peripheral driving TFT in the periphery circuit area;
wherein each of the active areas comprises a channel region, a source region, and a drain region, and the grain structure of a channel region of the peripheral driving TFT in the periphery circuit area is the same as the grain structure of the channel region of the switching TFT in each of the sub-pixels.
2. The method as claimed in claim 1 , wherein the method further comprises:
forming a gate insulating layer and a metal layer on the substrate sequentially; and
removing portions of the metal layer to form a plurality of gates of the switching TFTs and the driving TFTs.
3. The method as claimed in claim 1 , wherein the first crystallization process comprises a solid-phase crystallization (SPC) process.
4. The method as claimed in claim 3 , wherein the SPC process comprises a furnace annealing process, a rapid thermal process (RTP), or an alternating magnetic field crystallization (AMFC) process.
5. The method as claimed in claim 1 , wherein the second crystallization process comprises an excimer laser annealing (ELA) process.
6. The method as claimed in claim 5 , wherein the ELA process comprises a solid-state laser (SSL) or an excimer laser process.
7. The method as claimed in claim 1 , wherein the grain structure of the channel regions of the driving TFTs in the sub-pixels comprises a dendrite grain structure, and the grain structure of the channel regions of the switching TFTs in the sub-pixels comprises a columnar grain structure.
8. The method as claimed in claim 1 , wherein the standard deviation of the carrier mobility in the channel regions of the driving TFTs in the sub-pixels is smaller than the standard deviation of the carrier mobility in the channel regions of the switching TFTs in the sub-pixels.