Secure hashing device using multiple different SHA variants and related methods

1. A monolithic integrated circuit (IC) secure hashing device comprising:

a plurality of registers comprising a mode register configured to store a mode of operation value; and

a processor integrated with said plurality of registers and configured to

receive a message,

select a given secure hash algorithm (SHA) variant based upon the mode of operation value,

process the message using the given SHA variant from among a plurality of different SHA variants, the plurality of different SHA variants being based upon corresponding different block sizes of bits, and

cooperate with said plurality of registers for selecting the different block sizes of bits for the plurality of different SHA variants and for controlling SHA processing of the message;

said processor comprising

a message schedule generator configured to generate values for each round of SHA processing,

a round counter cooperating with said message schedule generator and configured to count the rounds of SHA processing, and

circuitry coupled to said message schedule generator and said plurality of registers, and configured to coordinate the SHA processing of the message, said circuitry comprising a finite state machine.

2. The monolithic IC secure hashing device according to claim 1 wherein said processor authenticates the message using the given SHA variant.

3. The monolithic IC secure hashing device according to claim 1 wherein the plurality of different SHA variants comprises SHA-224, SHA-256, SHA-384, and SHA-512.

4. The monolithic IC secure hashing device according to claim 1 wherein said plurality of registers cooperates with said processor for storing the received message.

5. The monolithic IC secure hashing device according to claim 1 wherein said plurality of registers cooperates with said processor for storing the processed message.

6. The monolithic IC secure hashing device according to claim 1 wherein said plurality of registers cooperates with said processor for providing a status of processing the message.

7. The monolithic IC secure hashing device according to claim 1 wherein the different block sizes of bits comprise 512 bits and 1024 bits.

8. The monolithic IC secure hashing device according to claim 1 wherein said processor and said plurality of registers are based upon a single field-programmable gate array (FPGA) device.

9. A monolithic integrated circuit (IC) secure hashing device comprising:

a plurality of registers comprising a mode register configured to store a mode of operation value, and a status register configured to store a hash operation status value; and

a processor integrated with said plurality of registers and configured to

receive a message,

select a given secure hash algorithm-2 (SHA-2) variant based upon the mode of operation value,

process the message using the given SHA-2 variant from among a plurality of different SHA-2 variants, the plurality of different SHA-2 variants being based upon corresponding different block sizes of bits,

update the hash operation status value based upon the processing of the message, and

cooperate with said plurality of registers for selecting the different block sizes of bits for the plurality of different SHA-2 variants and for controlling SHA-2 processing of the message;

said processor comprising

a message schedule generator configured to generate values for each round of SHA-2 processing,

a round counter cooperating with said message schedule generator and configured to count the rounds of SHA-2 processing, and

circuitry coupled to said message schedule generator and said plurality of registers, and configured to coordinate the SHA-2 processing of the message, said circuitry comprising a finite state machine.

10. The monolithic IC secure hashing device according to claim 9 wherein said processor authenticates the message using the given SHA-2 variant.

11. The monolithic IC secure hashing device according to claim 9 wherein the different SHA-2 variants comprise SHA-224, SHA-256, SHA-384, and SHA-512.

12. The monolithic IC secure hashing device according to claim 9 wherein said plurality of registers cooperates with said processor for storing the received message.

13. The monolithic IC secure hashing device according to claim 9 wherein said plurality of registers cooperates with said processor for storing the processed message.

14. A method of operating a monolithic integrated circuit (IC) secure hashing device comprising a plurality of registers comprising a mode register storing a mode of operation value, and a processor integrated with the plurality of registers, the method comprising:

receiving a message;

selecting a given secure hash algorithm (SHA) variant based upon the mode of operation value;

processing the message using the given SHA variant from among a plurality of different SHA variants, the plurality of different SHA variants being based upon corresponding different block sizes of bits;

selecting the different block sizes of bits for the plurality of different SHA variants and based upon the plurality of registers cooperating with the processor; and

using the plurality of registers integrated with the processor to control SHA processing of the message;

the processor comprising

a message schedule generator configured to generate values for each round of SHA processing,

a round counter cooperating with the message schedule generator and configured to count the rounds of SHA processing, and

circuitry coupled to the message schedule generator and the plurality of registers, and configured to coordinate the SHA processing of the message, the circuitry comprising a finite state machine.

15. The method according to claim 14 wherein the processing comprises authenticating the message using the given SHA variant.

16. The method according to claim 14 wherein the plurality of different SHA variants comprises a plurality of different SHA-2 variants.

17. The method according to claim 14 wherein the plurality of different SHA variants comprises SHA-224, SHA-256, SHA-384, and SHA-512.

18. The method according to claim 14 wherein the different block sizes of bits comprise 512 bits and 1024 bits.