X8R dielectric composition for use with nickel electrodes
View Patent ↗Multilayer ceramic chip capacitors which satisfy X8R requirements and which are compatible with reducing atmosphere sintering conditions so that non-noble metals such as nickel and nickel alloys thereof may be used for internal and external electrodes are made in accordance with the invention. The capacitors exhibit desirable dielectric properties (high capacitance, low dissipation factor, high insulation resistance), excellent performance on highly accelerated life testing, and very good resistance to dielectric breakdown. The dielectric layers comprise a barium titanate base material doped with other metal oxides such as BaO, Y 2 O 3 , ZrO 2 , SiO 2 , MgO, MnO, MoO 3 , CaO, Lu 2 O 3 , Yb 2 O 3 , or WO 3 in various combinations.
1. A multilayer ceramic chip capacitor comprising a fired collection of:
a. alternately stacked layers of a dielectric material comprising, prior to sintering, a blend of:
(i) BaTiO 3 , and the following, per 100 mole parts of BaTiO 3 :
(ii) about 0.01 to about 2 mole parts ZrO 2 ,
(iii) about 1 to about 6 mole parts BaCO 3 ,
(iv) about 0.05 to about 0.5 mole parts MnCO 3 ,
(v) about 0.01 to about 0.4 mole parts MoO 3 ,
(vi) about 0.05 to about 2.5 mole parts MgO,
(vii) about 0.5 to about 7 mole parts Y 2 O 3 , and
(viii) about 0.3 to about 4 mole parts SiO 2 , and
b. layers of an internal electrode material comprising a transition metal.
2. The multilayer ceramic chip capacitor of claim 1 , wherein the transition metal is other than Ag, Au, Pd or Pt.
3. The multilayer ceramic chip capacitor of claim 1 , wherein the capacitor has a dielectric constant greater than about 2000 and a dissipation factor less than about 2%, and wherein the capacitor meets EIA X8R standards.
4. The multilayer ceramic chip capacitor of claim 1 , wherein the transition metal is selected from the group consisting of Pd, Pt, a Pd—Ag alloy, and combinations thereof.
5. The multilayer ceramic chip capacitor of claim 4 , wherein the capacitor has a dielectric constant greater than about 2000 and a dissipation factor less than about 2%, and wherein the capacitor meets EIA X8R standards.
6. The multilayer ceramic chip capacitor of claim 1 , wherein
a. the dielectric material comprises:
(i) BaTiO 3 , and the following, per 100 mole parts of BaTiO 3 :
(ii) about 0.1 to about 1.75 mole parts ZrO 2 ,
(iii) about 2.5 to about 4.5 mole parts BaCO 3 ,
(iv) about 0.1 to about 0.4 mole parts MnCO 3 ,
(v) about 0.02 to about 0.3 mole parts MoO 3 ,
(vi) about 0.5 to about 2 mole parts MgO,
(vii) about 1 to about 6 mole parts Y 2 O 3 , and
(viii) about 1 to about 3 mole parts SiO 2 , and wherein
b. the transition metal is selected from the group consisting of Pd, Pt, and a Pd—Ag alloy.
7. The multilayer ceramic chip capacitor of claim 6 , wherein the capacitor has a dielectric constant greater than about 2000 and a dissipation factor less than about 2%, and wherein the capacitor meets EIA X8R standards.
8. A multilayer ceramic chip capacitor comprising a fired collection of
a. alternately stacked layers of a dielectric material comprising, prior to sintering, a blend of:
(i) BaTiO 3 , and the following, per 100 mole parts of BaTiO 3 :
(ii) about 1.5 to about 6 mole parts BaCO 3 ,
(iii) about 0.1 to about 0.5 mole parts MnCO 3 ,
(iv) about 0.5 to about 2 mole parts MgO,
(v) about 0.25 to about 3.5 mole parts Y 2 O 3 , and
(vi) about 1 to about 4 mole parts SiO 2 ,
(vii) about 0.5 to about 3.5 mole parts ZrO 2 , and
b. layers of an internal electrode material comprising a transition metal.
9. The multilayer ceramic chip capacitor of claim 8 , wherein the dielectric material further comprises about 0.5 to about 2.5 mole parts MoO 3 .
10. The multilayer ceramic chip capacitor of claim 8 , wherein the dielectric material further comprises about 0.01 to about 0.5 mole parts MoO 3 .
11. The multilayer ceramic chip capacitor of claim 8 , wherein the dielectric material further comprises about 0.5 to about 3.5 mole parts CaCO 3 .
12. The multilayer ceramic chip capacitor of claim 8 , wherein the dielectric material further comprises about 0.01 to about 0.5 mole parts CaCO 3 .
13. The multilayer ceramic chip capacitor of claim 8 , wherein the dielectric material further comprises about 0.5 to about 2.5 mole parts Yb 2 O 3 .
14. The multilayer ceramic chip capacitor of claim 8 , wherein the dielectric material further comprises about 2 to about 4 mole parts WO 3 .
15. A method of fabricating a multilayer ceramic chip capacitor having X8R characteristics comprising:
a. providing a dielectric material comprising:
i. BaTiO 3 , and the following, per 100 mole parts of BaTiO 3 :
ii. about 0.01 to about 2 mole parts ZrO 2 ,
iii. about 1 to about 6 mole parts BaCO 3 ,
iv. about 0.05 to about 0.5 mole parts MnCO 3 ,
v. about 0.01 to about 0.4 mole parts MoO 3 ,
vi. about 0.05 to about 2.5 mole parts MgO,
vii. about 0.5 to about 7 mole parts Y 2 O 3 , and
viii. about 0.3 to about 4 mole parts SiO 2 ,
b. forming alternately stacked layers of said dielectric material with layers of an internal electrode material comprising a transition metal, and
c. firing the stack in an atmosphere at a temperature sufficient to sinter the electrode material and fuse the dielectric material.
16. The method of claim 15 wherein the internal electrode material comprises a transition metal other than Ag, Au, Pd, or Pt, and wherein the atmosphere has a partial oxygen pressure of no more than about 10 −8 atmosphere.
17. The method of claim 15 wherein the internal electrode material comprises a transition metal selected from the group consisting of Pd, Pt, and a Pd—Ag alloy, and combinations thereof.
18. The method of claim 15 wherein the electrode paste comprises a Pd—Ag alloy having a weight ratio of about 99:1 to about 7:3.
19. The method of claim 15 wherein the firing is conducted in an atmosphere having a partial oxygen pressure of about 10 −12 to about 10 −8 atmosphere.