Thin film transistor panel and method of manufacturing the same
View Patent ↗After forming a signal line including aluminum, an upper layer of an oxide layer including aluminum that covers the signal line is formed in the same chamber and by using the same sputtering target as the signal line, or a buffer layer of an oxide layer including aluminum is formed in a contact hole exposing the signal line during the formation of the contact hole. Accordingly, the contact characteristic between an upper layer including indium tin oxide (“ITO”) or indium zinc oxide (“IZO”) and the signal line may be improved to enhance the adhesion therebetween while not increasing the production cost of the thin film transistor (“TFT”) array panel.
1. A thin film transistor array panel, comprising:
a substrate;
a gate line disposed on the substrate, including a gate electrode, and having a single-layered structure, and a storage line disposed on the substrate and having a single-layered structure;
a gate insulating layer disposed on the gate line;
a semiconductor layer disposed on the gate insulating layer;
a data line disposed on the semiconductor layer, including a source electrode, and having a single-layered structure;
a drain electrode disposed on the semiconductor layer, spaced apart from the source electrode, and having a single-layered structure;
a passivation layer disposed on the data line and the drain electrode, and having a first contact hole exposing the drain electrode;
a first buffer member in an upper surface of the drain electrode exposed through the first contact hole; and
a pixel electrode electrically connected to the drain electrode through the first buffer member.
2. The thin film transistor array panel of claim 1 , wherein the gate line and the data line comprise a same material.
3. The thin film transistor array panel of claim 2 , wherein the gate line and the data line comprise aluminum or an aluminum alloy.
4. The thin film transistor array panel of claim 3 , wherein the first buffer member comprises an aluminum oxide layer.
5. The thin film transistor array panel of claim 1 , wherein the first buffer member comprises a metal oxide layer.
6. The thin film transistor array panel of claim 3 , wherein the first buffer member comprises an aluminum oxide layer.
7. The thin film transistor array panel of claim 1 , further comprising
a blocking layer disposed between the semiconductor layer and the data line and drain electrode, and comprising nitrogen or a nitrogen compound.
8. The thin film transistor array panel of claim 1 , wherein the passivation layer and the gate insulating layer have a second contact hole exposing a portion of the storage line and the passivation layer has a third contact hole exposing a portion of the data line,
further comprising:
a second buffer member disposed in an upper surface of the storage line exposed through the second contact hole; and
a third buffer member disposed in an upper surface of the data line exposed through the third contact hole.
9. The thin film transistor array panel of claim 8 , wherein the storage line and the data line comprise a same material.
10. The thin film transistor array panel of claim 9 , wherein the storage line and the data line comprise aluminum or an aluminum alloy.
11. The thin film transistor array panel of claim 10 , wherein the first buffer member, the second buffer member, and the third buffer member comprise an aluminum oxide layer.
12. The thin film transistor array panel of claim 8 , wherein the first buffer member, the second buffer member, and the third buffer member comprise an aluminum oxide layer.
13. The thin film transistor array panel of claim 8 , further comprising
a blocking layer disposed between the semiconductor layer and the data line and drain electrode, and comprising nitrogen or a nitrogen compound.