Offset cancellation circuit and display device

1. An offset cancellation circuit provided in an operational amplifier, configured such that a first active load is connected to a first differential pair, the first differential pair comprises a first inversion input unit and a first non-inversion input unit, the first active load comprises a first and second transistors, and the first and second transistors each comprise a gate, comprising:

an input unit for inputting an input voltage to the first non-inversion input unit;

a first capacitance connected to the gate of the first transistor;

a second capacitance connected to the gate of the second transistor; and

a switch for setting a first time period and a second time period in connection states between the first and second transistors and the first and second capacitances, wherein

during the first time period, the connection states between the first and second transistors and the first and second capacitances are set so that a gate voltage of the first transistor is supplied to the first capacitance, and a gate voltage of the second transistor is supplied to the second capacitance,

during the second time period, the connection states between the first and second transistors and the first and second capacitances are set, so that the first and second capacitances can retain charges, and the second time period is an output time period of the operational amplifier.

2. The offset cancellation circuit constituted as claimed in claim 1 , further comprising:

a first output unit from which an output of the operational amplifier is outputted;

a third transistor combined with the first transistor, thereby constituting a first cascode circuit;

a fourth transistor comprising a drain and a source, the fourth transistor combined with the second transistor, thereby constituting a second cascode circuit;

a phase compensation capacitance provided between the source of the fourth transistor and the first output unit; and

a second output unit connected to the drain of the fourth transistor, the second output unit outputting an output of the first differential pair and an output of the first active load.

3. The offset cancellation circuit constituted as claimed in claim 1 , wherein

the operation amplifier is configured as a voltage follower, and

the offset cancellation circuit further comprises:

a first output unit from which an output from the operational amplifier is outputted;

a high-side transistor which is a drive transistor on the side of a high power supply of the first output unit; and

a low-side transistor which is a drive transistor on the side of a low power supply of the first output unit, and

during the first time period, the connection states between the first and second transistors, the first and second capacitances, the first output unit, the high-side transistor and the low-side transistor are set so that the input voltage is inputted to the input unit when the first inversion input unit, the first non-inversion input unit and the first output unit are connected to one another, and

during the second time period, the connection states between the first and second transistors, the first and second capacitances, the first output unit, the high-side transistor and the low-side transistor are set so that the second time period becomes the output time period of the operational amplifier.

4. A display device comprising:

a plurality of the offset cancellation circuits claimed in claim 1 ; and

a liquid crystal cell in which a light transmission factor varies or an organic EL cell in which a brightness level of light emission varies, depending on an output voltage of the offset cancellation circuit.