Method of manufacturing a thin film transistor array substrate

1. A method of manufacturing a thin film transistor array substrate, the method comprising:

(a) forming a structure comprising:

one or more gate lines with a plurality of gate electrodes for an array of thin film transistors;

a gate insulating film overlying the gate electrodes and providing gate dielectric for the thin film transistors;

a plurality of semiconductor regions over the gate insulating film, the semiconductor regions providing an active region for each thin film transistor;

one or more data lines;

for each thin film transistor, source/drain electrodes which partially overlie the thin film transistor's active region, wherein one of the source/drain electrodes of each thin film transistor is connected to a respective data line;

(b) forming a passivation film over the source/drain electrodes;

(c) forming a first photoresist pattern of a first photoresist over the passivation film, the first photoresist pattern comprising a first portion partially overlying at least one source/drain electrode of each thin film transistor and overlying each of a plurality of pixel electrode regions each of which is a region to be occupied by a pixel electrode, the first photoresist pattern comprising a second portion thicker than the first portion;

(d) patterning the passivation film using the first photoresist pattern as a mask;

(e) removing the first portion of the first photoresist pattern to form a second photoresist pattern of the first photoresist, the second photoresist portion forming protrusions around the pixel electrode regions;

(f) forming a transparent conductive overlying the second photoresist pattern and being recessed in each pixel electrode region;

(g) forming a masking pattern over the transparent conductive film in each pixel electrode region, the masking pattern's top surface being below a top of the transparent conductive film over the second photoresist pattern;

(h) patterning the transparent conductive film using the masking pattern as a mask to form each said pixel electrode; and

(i) removing the masking pattern.

2. The method of claim 1 , wherein forming said structure comprises:

depositing the gate insulating film, then an intrinsic amorphous silicon film, then an n+ amorphous silicon film, and then a data conductor film;

forming a third photoresist pattern over the data conductor film, wherein the third photoresist pattern comprises a third portion over a channel region of each thin film transistor and a fourth portion over the source/drain electrodes, the fourth portion being thicker than the third portion;

etching the data conductor film, then the n+ amorphous silicon film, and then the intrinsic silicon film using the third photoresist pattern as a mask to form the one or more data lines, an n+ semiconductor pattern, and an intrinsic semiconductor pattern;

removing the third portion of the third photoresist pattern to transform the third photoresist pattern into a fourth photoresist pattern; and

etching the data conductor film and the n+ semiconductor film using the fourth photoresist pattern as a mask to form the source/drain electrodes and ohmic contacts which underlie and contact the source and drain electrodes and which overlie and contact the thin film transistors' active regions.

3. The method according to claim 2 , further comprising forming a storage electrode line of the same material and film as the one or more gate lines, wherein the storage electrode line runs parallel with the one or more gate lines.

4. The method according to claim 3 , wherein the masking pattern is formed from a layer deposited by spin coating, slit coating, or inkjet printing.

5. The method according to claim 4 , wherein the passivation film comprises a first passivation layer and a second passivation layer.

6. The method according to claim 2 , wherein the masking pattern is formed from a layer deposited by spin coating, slit coating, or inkjet printing.

7. The method according to claim 6 , wherein the passivation film comprises a first passivation layer and a second passivation layer.

8. The method according to claim 1 , further comprising forming a storage electrode line of the same material and film as the one or more gate lines, wherein the storage electrode line runs parallel with the one or more gate lines.

9. The method according to claim 8 , wherein the masking pattern is formed from a layer deposited by spin coating, slit coating, or inkjet printing.

10. The method according to claim 9 , wherein the passivation film comprises a first passivation layer and a second passivation layer.

11. The method according to claim 8 , wherein the passivation film comprises a first passivation layer and a second passivation layer.

12. The method according to claim 1 , wherein the masking pattern is formed from a layer deposited by spin coating, slit coating, or inkjet printing.

13. The method according to claim 12 , wherein the passivation film comprises a first passivation layer and a second passivation layer.

14. The method according to claim 1 wherein the masking pattern is formed without a mask process.

15. The method according to claim 1 wherein the masking pattern is not defined by selective deposition of any material and is not defined by selective removal of any material.

16. The method of claim 1 wherein the masking pattern is defined by the second photoresist pattern.

17. The method according to claim 1 wherein each pixel electrode overlies the gate insulating film.