Processing of coherent and incoherent accesses at a uniform cache
View Patent ↗Each cacheline of a unified cache storing information is marked as incoherent if the information was acquired incoherently or marked as coherent if the information was acquired coherently. A subsequent incoherent read access to a cacheline can result in a cache hit and a return of the cached information regardless of whether the cacheline is marked as coherent or incoherent. However, a subsequent coherent read access to a cacheline marked as incoherent will be returned as a cache miss regardless of whether the cacheline includes information sought by the coherent read access. In response to a cache miss for a coherent read access, a global snoop is initiated so as to query all other target components within the same coherency domain. In contrast, a cache miss resulting from an incoherent read access is processed using a non-global snoop to a limited set of one or a few target components in the coherency domain.
1. In a processing device comprising a cache configured to store both instruction information and data information, a method comprising:
receiving, at the cache, a first read access that is indexed to a first cacheline;
determining whether the first cacheline is marked as coherent or incoherent;
in response to determining the first read access is a coherent read access, processing the first read access as a cache miss at a processor core of the processing device in response to determining the first cacheline is marked as incoherent; and
in response to determining the first read access is an incoherent read access, processing the first read access as a cache hit at the processor core regardless of whether the first cacheline is marked as coherent or incoherent.
2. The method of claim 1 , further comprising:
in response to determining the first read access is a coherent read access:
processing the first read access as a cache hit at the processor core in response to determining the first cacheline is marked as coherent.
3. The method of claim 1 , further comprising:
in response to determining the read access is a coherent read access:
processing the first read access as a cache hit at the processor core in response to determining the first cacheline is marked as coherent.
4. The method of claim 1 , wherein processing the first read access as a cache miss in response to determining the first cacheline is marked as incoherent comprises:
performing a global snoop of target components of a coherency domain of the processing device to acquire for the processor core information sought by the coherent read access.
5. The method of claim 1 , further comprising:
receiving, at the cache, a second read access; and
in response to determining the second read access is not indexed to a cacheline of the cache:
performing a global snoop of target components of a coherency domain of the processing device to acquire for the processor core information sought by the second read access in response to determining the second read access is a coherent read access; and
performing a non-global snoop of a subset of the target components of the coherency domain of the processing device to acquire for the processor core information sought by the second read access in response to determining the second read access is an incoherent read access.
6. The method of claim 1 , further comprising:
receiving, at the cache, a write access to store information to the first cacheline;
marking the first cacheline as incoherent in response to determining the write access is an incoherent write access; and
marking the first cacheline as coherent in response to determining the write access is a coherent write access.
7. The method of claim 6 , further comprising:
determining the write access is a coherent write access when the information comprises data information associated with a data load operation or a data store operation; and
determining the write access is an incoherent write access when the information comprises instruction information associated with an instruction fetch operation.
8. The method of claim 6 , wherein:
marking the first cacheline as incoherent comprises storing a first bit value at a predetermined field associated with the first cacheline; and
marking the first cacheline as coherent comprises storing a second bit value at the predetermined field.
9. The method of claim 1 , wherein the cache comprises a backside cache of the processor core.
10. In a processing device comprising a cache configured to store both instruction information and data information, a method comprising:
processing a coherent read access as a cache miss for a processor core of the processing device in response to determining that a first cacheline that is indexed by the coherent read access is marked as incoherent regardless of whether the first cacheline includes information sought by the coherent read access; and
processing an incoherent read access as a cache hit at the cache in response to determining that a second cacheline is indexed by the incoherent read access regardless of whether the second cacheline is marked as coherent or incoherent.
11. The method of claim 10 , further comprising:
processing the incoherent read access as a cache miss at the cache in response to determining that the incoherent read access does not index any cacheline of the cache.
12. The method of claim 11 , wherein:
processing the coherent read access as a cache miss comprises performing a global snoop of target components of a coherency domain of the processing device to acquire information sought by the coherent read access for the processor core; and
processing the incoherent read access as a cache miss comprises performing a non-global snoop of a subset of the target components of the coherency domain to acquire information sought by the incoherent read access for the processor core.
13. The method of claim 10 , further comprising:
determining the first cacheline is marked as incoherent based on a bit value stored in a first field of the cache that is associated with the first cacheline; and
determining the second cacheline is marked as coherent based on a bit value stored in a second field of the cache that is associated with the second cacheline.
14. A processing device comprising:
a processor core; and
a unified cache comprising:
a cacheline; and
access control logic to:
process a read access indexed to the cacheline;
signal a cache miss to the processor core in response to determining the read access is a coherent read access and the cacheline is marked as incoherent; and
signal a cache hit to the processor core in response to determining the read access is an incoherent read access regardless of whether the cacheline is marked as incoherent or coherent.
15. The processing device of claim 14 , wherein the processor core is to:
initiate a global snoop of target components of a coherency domain of the processing device to acquire information sought by the read access for the processor core in response to the access control logic signaling a cache miss and the read access comprising a coherent read access; and
initiate a non-global snoop of a subset of the target components of the coherency domain to acquire information sought by the read access for the processor core in response to the access control logic signaling a cache miss and the read access comprising an incoherent read access.
16. The processing device of claim 14 , wherein the unified cache further comprises:
an incoherency status field associated with the cacheline, the incoherency status field storing a bit value marking the cacheline as either coherent or incoherent.
17. The processing device of claim 16 , wherein the access control logic further is to:
receive a write access indexed to the cacheline;
store a first bit value to the incoherency status field in response to determining the write access is an incoherent write access; and
store a second bit value to the incoherency status field in response to determining the write access is a coherent write access.
18. The processing device of claim 17 , wherein the access control logic is to:
determine the write access is a coherent write access when information associated with the write access comprises data information associated with a data load operation or a data store operation; and
determining the write access is an incoherent write access when the information comprises instruction information associated with an instruction fetch operation.
19. The processing device of claim 14 , wherein the unified cache comprises a backside cache of the processor core.