Testing wiring structure and method for forming the same
View Patent ↗The invention provides a testing wiring structure of a thin film transistor (TFT) motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard and a method for forming the same. The testing wiring structure comprises a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring. The gate layer metallic testing wiring are connected to a portion of the plurality of signal lines and the drain layer metallic testing wiring both are connected to remaining portion of the plurality of signal lines. A pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring. The pixel electrode layer testing wiring is electrically connected to the drain layer metallic testing wiring to be a redundant testing wiring of the drain layer metallic testing wiring.
1. A testing wiring structure of a thin film transistor (TFT) array motherboard for applying signals to a plurality of signal lines in a pixel region on the motherboard, comprising a gate layer metallic testing wiring and a drain layer metallic testing wiring that is over and intersects the gate layer metallic testing wiring, the gate layer metallic testing wiring being connected to a portion of the plurality of signal lines, and the drain layer metallic testing wiring being connected to remaining portion of the plurality of signal lines,
wherein a pixel electrode layer testing wiring is further provided over the drain layer metallic testing wiring in an intersecting region where the drain layer metallic testing wiring intersects the gate layer metallic testing wiring, and
the pixel electrode layer testing wiring is electrically connected to the drain layer metallic testing wiring to be a redundant testing wiring of the drain layer metallic testing wiring.
2. The testing wiring structure of a TFT array motherboard according to claim 1 , wherein a passivation layer is formed between the pixel electrode layer testing wiring and the drain layer metallic testing wiring, and both ends of the pixel electrode layer testing wiring are connected through via holes formed in the passivation layer to the drain layer metal portion of the drain layer metallic testing layer.
3. The testing wiring structure of a TFT array motherboard according to claim 1 , wherein the pixel electrode testing wiring and the drain layer metallic testing wiring each extend in a first direction, the gate layer metallic testing wiring extends in a second direction, and the pixel electrode layer testing wiring is laterally separated from the drain layer metallic testing wiring in the second direction in the intersecting region, the second direction being substantially perpendicular to the first direction.
4. The testing wiring structure of a TFT array motherboard according to claim 1 , wherein the signal lines are gate lines or data lines in the pixel region.