Multi-core device with optimized memory configuration

1. A multi-core device comprising:

at least two cores each operable to execute instructions embodied as software stored on a persistent memory means, wherein at least one of said at least two cores is associated with a primary memory of said memory means, said primary memory being random access memory (“RAM”),

a first software portion stored in said primary memory to be executed by said at least one of said at least two cores once said first software portion has been transferred from said primary memory along with data associated with said first software portion, and

a memory interface interposed between and coupled to said RAM and to at least one of said at least two cores, for allowing said at least one of said at least two cores to execute said first software portion stored in said primary memory and to access the data associated with said first software portion,

wherein another one of said at least two cores is associated with a secondary memory that is a part of said memory means and is operable to persistently store software to be executed by each of said at least two cores and wherein said another one of said at least two cores is operable to transfer a software portion stored in the secondary memory to be stored in the primary memory

wherein transferring said first software portion to the primary memory is conducted through a first memory interface, a first core, a second core and a second memory interface, in turn.

2. The multi-core device according to claim 1 , wherein said secondary memory is a flash Read Only Memory (“ROM”).

3. The multi-core device according to claim 1 , wherein said another one of said at least two cores is associated with

an external RAM memory which is part of said memory means, is coupled to said secondary memory and is operable of dynamically storing a second software portion to be executed by said another one of said cores upon said second software portion being transferred from said secondary memory, and

another memory interface interposed between and coupled to said external RAM memory and said another one of said cores, said another memory interface operable to allow said another one of said cores to execute the second software portion stored in said external memory.

4. The multi-core device according to claim 1 , wherein said another one of said at least two cores further comprises an internal RAM memory coupled to said secondary memory and operable to accept and store a second software portion transferred from said secondary memory wherein said second software portion is to be executed by said another one of said cores, said internal memory being part of said memory means.

5. The multi-core device according to claim 1 , further comprising an external memory coupled to at least one of said at least two cores and operable for storing said software portions prior to their transfer to said primary memory.

6. The multi-core device according to one of claim 1 wherein said primary memory is a Magnetic Random Access Memory.

7. The multi-core device according to claim 1 wherein said primary memory includes characteristics equivalent to or better than Magnetic Random Access Memories.

8. The multi-core device according to claim 1 wherein said at least two cores are utilized in a piece of electronic equipment.

9. The multi-core device according to claim 8 wherein said piece of electronic equipment is selected from a group consisting of a mobile telephone, a computer, a portable computer, a game player, an audio player, a video player, a television, a set-top box and a personal digital assistant.

10. The multi-core device according to claim 8 wherein transfer of said durably stored software portion from said secondary memory to said primary memory occurs during a first boot of said piece of electronic equipment.

11. A method for multi-core processing of software in an electronic device, the method comprising:

storing in a secondary memory a plurality of instructions embodied as different software portions;

responsive to a first boot of said electronic device, transferring a first software portion from said secondary memory to a primary memory, wherein a second software portion is retained in said secondary memory;

accessing said first software portion by a first core and said second software portion by a second core from said primary memory and said secondary memory, respectively and autonomously; and

executing at said first core and at said second core said first software portion and said second software portion respectively and autonomously,

wherein transferring said first software portion to the primary memory is conducted through a first memory interface, a first core, a second core and a second memory interface, in turn.

12. The method of claim 11 wherein said first software portion is transferred to the primary memory directly.

13. The method of claim 11 wherein said primary memory and said secondary memory are operable for persistent storage.

14. The method of claim 13 wherein said primary memory is Random Access Memory.

15. The method of claim 14 wherein said primary memory is flash memory.

16. The method of claim 11 wherein said secondary memory is Read Only Memory.

17. The method of claim 11 further comprising storing the second software portion in an external memory coupled to said secondary memory.

18. The method of claim 11 further comprising storing the second software portion in an internal memory associated with said second core.