Spike noise eliminating circuit, digital system using the same, and IIC bus
View Patent ↗There is provided a spike noise eliminating circuit that can eliminate reliably spike noise having a predetermined pulse width or smaller and transmit and output precisely a signal having a pulse width larger than the predetermined width. Spike noise in the input signal is eliminated by: detecting a coincidence in level of the input signal and a first delay signal obtained by delaying the input signal by a maximum pulse width of noise to be eliminated as a delay amount; and sampling the input signal or a second delay signal obtained by delaying the input signal by a certain period of time based on a signal obtained as a result of detecting the coincidence in level.
1. A spike noise eliminating circuit comprising:
a first delay gate that delays an input signal by a predetermined period of time;
an arithmetic logic circuit that performs an exclusive logical operation on an output signal of the first delay gate and the input signal;
a second delay gate that delays an output signal of the arithmetic logic circuit; and
a flip flop circuit that receives the input signal at a data terminal and receives an output signal of the second delay gate at a clock terminal.
2. A digital system comprising:
the spike noise eliminating circuit according to claim 1 ; and
a digital block for video display control that processes an output signal of the spike noise eliminating circuit as a synchronization signal.
3. An IIC bus comprising:
the spike noise eliminating circuit according to claim 1 ; and
an IIC bus transmission/reception control part that processes an output signal of the spike noise eliminating circuit as a communication signal.
4. A spike noise eliminating circuit comprising:
a first delay gate that delays an input signal by a predetermined period of time;
an arithmetic logic circuit that performs an exclusive logical operation on an output signal of the first delay gate and the input signal;
a second delay gate that delays an output signal of the arithmetic logic circuit; and
a flip flop circuit that receives an output signal of the first delay gate at a data terminal and receives an output signal of the second delay gate at a clock terminal.
5. A spike noise eliminating circuit comprising:
a first delay gate that delays an input signal by a predetermined period of time;
an arithmetic logic circuit that performs an exclusive logical operation on an output signal of the first delay gate and the input signal;
a second delay gate that delays an output signal of the arithmetic logic circuit;
a third delay gate that delays the input signal by a certain period of time; and
a flip flop circuit that receives an output signal of the third delay gate at a data terminal and receives an output signal of the second delay gate at a clock terminal.