Nonvolatile memory element array with storing layer formed by resistance variable layers

1. A nonvolatile memory element array comprising a plurality of nonvolatile memory elements, each of the nonvolatile memory elements including:

a lower electrode provided on a substrate;

an upper electrode provided above the lower electrode;

a resistance variable layer sandwiched between the lower electrode and the upper electrode;

wherein the resistance variable layer includes a high-resistance layer and a low-resistance layer;

wherein the resistance variable layer has a characteristic in which a resistance value of the resistance variable layer is increased or reduced by applying electric pulses between the lower electrode and the upper electrode; and

wherein the resistance variable layer is connected to the upper electrode only at a portion of a main surface of the upper electrode or connected to the lower electrode only at a portion of a main surface of the lower electrode;

and

a first interlayer insulating layer provided on the substrate to cover the lower electrode, wherein a first contact hole is provided on the lower electrode to penetrate through the first interlayer insulating layer;

wherein the low-resistance layer is provided inside the first contact hole such that low-resistance layers in adjacent nonvolatile memory elements are isolated from each other;

and wherein the high-resistance layer is provided outside the first contact hole to have a size larger than a diameter of the first contact hole.

2. The nonvolatile memory element array according to claim 1 , wherein

the low-resistance layer is connected to the high-resistance layer only at a portion of a main surface of the high-resistance layer.

3. The nonvolatile memory element array according to claim 1 , which is being a cross-point type nonvolatile memory element,

wherein a plurality of lower electrodes are arranged to extend in parallel with each other within a first plane which is parallel to a main surface of the substrate;

wherein a plurality of upper electrodes are arranged to extend in parallel with each other within a second plane which is parallel to the first plane and to three-dimensionally cross the lower-electrodes;

wherein the resistance variable layer is provided between the lower electrode and the upper electrode so as to correspond to each of three-dimensional cross points of the plurality of lower electrodes and the plurality of upper electrodes; and

wherein the nonvolatile memory element is provided to correspond to each of the three-dimensional cross points.

4. The nonvolatile memory element array according to claim 1 , wherein the high-resistance layer in adjacent nonvolatile memory elements is provided to extend continuously.

5. The nonvolatile memory element array according to claim 1 , wherein

the low-resistance layer has a resistivity which is not lower than 1×10 −3 Ωcm and not higher than 2×10 −2 Ωcm.

6. The nonvolatile memory element array according to claim 1 , wherein the high-resistance layer has a resistivity which is not lower than 0.13 Ωcm and not higher than 250 Ωcm.

7. The nonvolatile memory element array according to claim 1 , wherein the low-resistance layer is a layer containing Fe 3 O 4 .

8. The nonvolatile memory element array according to claim 1 , wherein the high-resistance layer is a layer containing at least one material which is selected from a group consisting of Fe 2 O 3 , ZnFe 2 O 4 , MnFe 2 O 4 , and NiFe 2 O 4 .

9. The nonvolatile memory element array according to claim 1 , further comprising:

an embedded insulating layer which is formed by an insulator embedded in the low-resistance layer;

wherein an upper surface of the embedded insulating layer is connected to a portion of a lower surface of the high-resistance layer, and a side surface and a lower surface of the embedded insulating layer are covered with the low-resistance layer.