Method and apparatus for providing control signaling
View Patent ↗An approach is provided for an efficient control signaling associated with an error control scheme. A determination is made whether data has been properly received according to an error control scheme. A first pilot sequence representing an acknowledgement is generated if the data is properly received. A second pilot sequence representing a negative acknowledgement is generated if the data is not properly received. A frame including either the first pilot sequence or the second pilot sequence is output.
1. A method comprising:
determining whether data has been properly received according to an error control scheme; encoding a pilot sequence by a first cover sequence if the data is properly received; encoding the pilot sequence by a second cover sequence if the data is not properly received; and multiplexing the encoded pilot sequences with channel quality indicator bits into a common sub-frame, wherein a length of at least the first and second cover sequences is equal to two when there are two pilot transport blocks in one time slot and three when there are three pilot transport blocks in one time slot.
2. A method according to claim 1 , wherein the first cover sequence is represented by an X-OR operation of ones, and the second cover sequence is represented by an X-OR operation of alternating ones and zeros.
3. A method according to claim 1 , wherein the pilot sequence comprises a ZAC (Zero Automatic Correlation) or CAZAC (Constant Amplitude and Zero Automatic Correlation) based pilot sequence.
4. A method according to claim 1 , further comprising:
performing cyclic shift separation between multiple pilot sequences sharing the same frequency and time resource.
5. An apparatus comprising:
an error control logic configured to determine whether data has been properly received according to an error control scheme; an encoder configured to encode a first pilot sequence by a first cover sequence if the data is properly received, and to encode the pilot sequence by a second cover sequence if the data is not properly received; and a multiplexer configured to multiplex the encoded pilot sequences with channel quality indicator bits into a common sub-frame, wherein a length of at least the first and second cover sequence is equal to two when there are two pilot transport blocks in one time slot and three when there are three pilot transport blocks in one time slot.
6. An apparatus according to claim 5 , wherein the second cover sequence is shared by a discontinuous transmission state.
7. An apparatus according to claim 5 , wherein the first cover sequence is represented by an X-OR operation of ones, and the second cover sequence is represented by an X-OR operation of alternating ones and zeros.
8. An apparatus according to claim 5 , wherein the pilot sequence comprises a ZAC (Zero Automatic Correlation) or CAZAC (Constant Amplitude and Zero Automatic Correlation) based pilot sequence.
9. An apparatus according to claim 5 , wherein the sub-frame is transmitted over an uplink of a network, wherein the network is compliant with a Long Term Evolution architecture.
10. An apparatus according to claim 5 , wherein the channel quality indicator bits correspond to an uplink of a network channel.
11. An apparatus according to claim 5 , wherein a cyclic shift separation is performed between multiple pilot sequences sharing the same frequency and time resource.
12. A method comprising:
determining a first cover sequence and a second cover sequence; and correlating a received sub-frame with at least one of the first cover sequence and the second cover sequence to determine presence of, respectively, an acknowledgement message or a negative acknowledgement message, wherein the received sub-frame specifies acknowledgement signaling for transmitted data according to an error control scheme and the received sub-frame further specifies channel quality indicator bits, wherein a length of at least the first and second cover sequence is equal to two when there are two pilot transport blocks in one time slot and three when there are three pilot transport blocks in one time slot.
13. An apparatus comprising:
a processor configured to determine a first cover sequence and a second cover sequence; and a channel estimator configured to correlate a received sub-frame with at least one of the first cover sequence and the second cover sequence to determine presence of, respectively, an acknowledgement message or a negative acknowledgement message, wherein the received sub-frame specifies acknowledgement signaling for transmitted data according to an error control scheme and the received sub-frame further specifies channel quality indicator bits, wherein a length of at least the first and second cover sequence is equal to two when there are two pilot transport blocks in one time slot and three when there are three pilot transport blocks in one time slot.
14. An apparatus according to claim 13 , wherein the received sub-frame comprises a ZAC (Zero Automatic Correlation) or CAZAC (Constant Amplitude and Zero Automatic Correlation) based pilot sequence.
15. A non-transitory computer-readable medium bearing computer program code embodied therein for use with a computer, the computer program code comprising: code for determining whether data has been properly received according to an error control scheme; code for encoding a pilot sequence by a first cover sequence if the data is properly received and encoding the pilot sequence by a second cover sequence if the data is not properly received; and code for multiplexing the encoded pilot sequence with channel quality indicator bits into a common sub-frame, wherein a length of at least the first and second cover sequences is equal to two when there are two pilot transport blocks in one time slot and three when there are three pilot transport blocks in one time slot.