Nonvolatile semiconductor memory apparatus and manufacturing method thereof

1. A nonvolatile semiconductor memory apparatus comprising:

a semiconductor substrate;

an active element forming region provided on said semiconductor substrate and including a plurality of active elements;

a wire forming region which is provided on said active element forming region to electrically connect the active elements and includes two or more semiconductor electrode wires and a wire region insulating layer covering the semiconductor electrode wires;

a memory portion forming region which is provided above said wire forming region and provided with memory portions arranged in matrix, a resistance value of each of the memory portions changing according to electric pulses applied, said memory portion forming region including an upper electrode wire, a resistance variable layer, a lower electrode wire, and a memory region insulating layer covering the upper electrode wire, the resistance variable layer, and the lower electrode wire; wherein the lower electrode wires are formed in a stripe shape above said wire forming region via a first insulating layer serving as the memory region insulating layer; the resistance variable layers are embedded to fill contact holes formed in an interlayer insulating layer serving as the memory region insulating layer such that the resistance variable layers are respectively connected to the lower electrode wires; the upper electrode wires are formed in a stripe shape on the interlayer insulating layer such that the upper electrode wires are respectively connected to the resistance variable layers and respectively cross the lower electrode wires; the memory portions are each constituted by the lower electrode wire, the resistance variable layer, and the upper electrode wire corresponding to a region where the lower electrode wire and the upper electrode wire cross each other;

a first oxygen barrier layer which is interposed between said memory portion forming region and said wire forming region and extends continuously over an entire of said memory portion forming region to block oxygen for at least the entire of said memory portion forming region; and

a second oxygen barrier layer provided between the interlayer insulating layer and the upper electrode wires

wherein an insulating material used for the wire region insulating layer has a dielectric constant smaller than a dielectric constant of an insulating material used for the memory region insulating layer;

when the resistance variable layers are arranged like islands to respectively correspond to the memory portions in a planar view, a region surrounding by a shortest line and in an annular form an outer periphery of the resistance variable layers arranged at an outermost side corresponds to said memory portion forming region.

2. The nonvolatile semiconductor memory apparatus according to claim 1 , further comprising:

an oxygen barrier separating film provided inside each of the contact holes such that said oxygen barrier separating film is interposed between the resistance variable layer and the interlayer insulating layer.

3. The nonvolatile semiconductor memory apparatus according to claim 2 ,

wherein said second oxygen barrier layer is made of a material forming said oxygen barrier separating film.

4. The nonvolatile semiconductor memory apparatus according to claim 1 ,

wherein plural layers of the memory portion forming regions are stacked to form a layer structure above said wire forming region.

5. The nonvolatile semiconductor memory apparatus according to claim 1 ,

wherein the lower electrode wires and the upper electrode wires are respectively connected to the semiconductor electrode wires in a region different from said memory portion forming region.

6. The nonvolatile semiconductor memory apparatus according to claim 1 , further comprising:

wire insulating layers which are respectively provided between adjacent lower electrode wires and between adjacent upper electrode wires and are serving as the memory region insulating layer;

wherein an insulating material used for at least one of the wire insulating layers has a dielectric constant smaller than a dielectric constant of an insulating material used for the interlayer insulating layer.

7. The nonvolatile semiconductor memory apparatus according to claim 6 ,

wherein the lower electrode wires are embedded in the first insulating layer such that main surfaces thereof are exposed, and the first insulating layer is said wire insulating layer provided between adjacent lower electrodes.

8. The nonvolatile semiconductor memory apparatus according to claim 1 ,

wherein at least one of an interval between adjacent lower electrode wires and an interval between adjacent upper electrode wires is smaller than a thickness of the interlayer insulating layer.

9. The nonvolatile semiconductor memory apparatus according to claim 1 ,

wherein the resistance material layer is made of a material which is an oxide containing iron.

10. The nonvolatile semiconductor memory apparatus according to claim 1 ,

wherein the interlayer insulating layer is silicon oxide layer formed using a tetraethyloxysilane-ozone based gas, or fluorosilicate glass.

11. The nonvolatile semiconductor memory apparatus according to claim 6 ,

wherein the wire insulating layer is silicon carbon nitride layer or silicon oxycarbite layer.

12. The nonvolatile semiconductor memory apparatus according to claim 1 ,

wherein the first oxygen barrier layer is a silicon nitride layer, a silicon oxynitride layer, an alumina layer, a tantalum oxide layer, a titanium oxide layer, a hafnium oxide layer or a zircon oxide layer.

13. A method of manufacturing a nonvolatile semiconductor memory apparatus comprising:

a step for forming an active element forming region including a plurality of active elements on a semiconductor substrate;

a step for forming a wire forming region on the active element forming region to electrically connect the active elements such that plural layers of two or more semiconductor electrode wires and a wire region insulating layer covering the semiconductor electrode wires are formed;

a step for forming a first oxygen barrier layer on the wire forming region; and

a step for forming a memory portion forming region on the first oxygen barrier layer, including forming lower electrode wires, forming resistance variable layers on the lower electrode wires, forming upper electrode wires on the resistance variable layers; and forming a memory region insulating layer covering the lower electrode wires, the resistance variable layers and the upper electrode wires to arrange memory portions in matrix, a resistance value of the memory portions changing according to electric pulses applied; wherein said step for forming the memory portion forming region includes: a step for forming a first insulating layer serving as the memory region insulating layer; a step for forming stripe-shaped lower electrode wires on the first insulating layer; a step for forming an interlayer insulating layer serving as the memory region insulating layer so as to cover the lower electrode wires and the first insulating layer; a step for forming contact holes above the first oxygen barrier layer and in the interlayer insulating layer on the lower electrode wires such that the lower electrode wires are exposed; a step for embedding the resistance variable layers to fill the contact holes such that the resistance variable layers are respectively connected to the lower electrode wires; and a step for forming stripe-shaped upper electrode wires on the interlayer insulating layer such that the upper electrode wires are respectively connected to the resistance variable layers and respectively cross the lower electrode wires; a step for forming a second oxygen barrier layer between the interlayer insulating layer and the upper electrode wires;

wherein in said step for forming the first oxygen barrier layer, the first oxygen barrier layer is formed to extend continuously over at least an entire of the memory portion forming region;

an insulating material used for the wire region insulating layer has a dielectric constant smaller than a dielectric constant of an insulating material used for the memory region insulating layer;

when the resistance variable layers are formed like islands so as to respectively correspond to regions where the lower electrode wires respectively cross the upper electrode wires in said step for embedding the resistance variable layer, a region surrounding by a shortest line and in an annular form an outer periphery of the resistance variable layers arranged at an outermost side corresponds to the memory portion forming region.

14. The method of manufacturing the nonvolatile semiconductor memory apparatus according to claim 13 ,

wherein the lower electrode wires and the upper electrode wires are connected to the semiconductor electrode wires in a region different from the memory portion forming region.

15. The method of manufacturing the nonvolatile semiconductor memory apparatus according to claim 13 , further comprising:

a step for repeating the step for forming the memory portion forming region to stack above the wire forming region plural layers of the memory portion forming regions.