IP Library Granted Patent US 8,143,144
Granted Patent B2
US 8,143,144 · App. 12/451,898 · Granted Mar 27, 2012

Semiconductor nanowire and its manufacturing method

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Quick Facts
Patent No.
US 8,143,144
App. No.
12/451,898
Granted
Mar 27, 2012
Kind
B2
Abstract

A method for fabricating a semiconductor nanowire that has first and second regions is provided. A catalyst particle is put on a substrate. A first source gas is introduced, thereby growing the first region from the catalyst particle via a vapor-liquid-solid phase growth. A protective coating is formed on a sidewall of the first region, and a second source gas is introduced to grow the second region extending from the first region via the liquid-solid-phase growth.

Claims (39)

1. A method for fabricating a semiconductor nanowire that has first and second regions, the method comprising:

putting a catalyst particle on a substrate;

growing the first region from the catalyst particle with a vapor-liquid-solid phase (VLS) grower;

forming a protective coating on a sidewall of the first region; and

growing the second region extending from the first region with the VLS grower.

2. The method of claim 1 , wherein a conductivity type of the first region is one of N and P types and a conductivity type of the second region is an other of N and P types.

3. The method of claim 1 , wherein a conductivity type of the first region is the same as a conductivity type of the second region, and wherein an electrical conductivity of the second region is lower than an electrical conductivity of the first region.

4. The method of claim 1 , wherein the catalyst particle comprises one of a metal and an alloy of a metal and further comprises a semiconductor.

5. The method of claim 1 , wherein the second region comprises a semiconductor material doped with a dopant element.

6. The method of claim 5 , wherein at a growth temperature of the second region, a solid solubility of the dopant element with respect to the catalyst particle is at most 1×10 19 atoms/cm 3 .

7. The method of claim 6 , wherein the first and second regions comprise a semiconductor material that includes at least one element selected from a group consisting of Si, Ge and C.

8. The method of claim 5 , wherein the dopant element comprises at least one element selected from a group consisting of B, P, As and Sb.

9. The method of claim 1 , wherein, when growing the second region, a constituent element of the second region diffuses through the protective coating and does not diffuse to the first region.

10. The method of claim 9 , wherein the protective coating includes at least one film selected from a group consisting of a silicon dioxide film, a silicon oxynitride film and a silicon nitride film.

11. The method of claim 1 , wherein a bandgap of the first region is different from a bandgap of the second region.

12. The method of claim 11 , wherein the second region comprises at least two different elements and wherein at a growth temperature of the second region, a solid solubility of at least one of the at least two different elements of the second region with respect to the catalyst particle is at most 1×10 19 atoms/cm 3 .

13. The method of claim 1 , wherein the protective coating is formed by thermally oxidizing the first region.

14. A semiconductor nanowire comprising:

a first region including a dopant in a concentration of at least 1×10 19 atoms/cm 3 ;

a second region, arranged continuously with the first region in a longitudinal direction thereof and including one of a first dopant in a concentration of at most 1×10 18 atoms/cm 3 and no dopant; and

a third region arranged continuously with the second region in the longitudinal direction thereof and including a second dopant in a concentration of at least 1×10 19 atoms/cm 3 .

15. A semiconductor device with the semiconductor nanowire of claim 14 , comprising:

a source electrode connected to the first region of the semiconductor nanowire;

a drain electrode connected to the third region of the semiconductor nanowire;

a gate electrode facing the second region of the semiconductor nanowire; and

a gate insulating film arranged between the second region and the gate electrode.

16. A semiconductor nanowire, comprising:

a first region including a dopant;

a second region having a lower dopant concentration than the first region and arranged continuously with the first region in a longitudinal direction thereof;

a third region, which has having a higher dopant concentration than the second region and arranged continuously with the second region in the longitudinal direction thereof;

a first sidewall arranged on a side surface of the first region and including a first polycrystalline material; and

a second sidewall arranged on a side surface of the third region and including a second polycrystalline material,

wherein the first sidewall and the second sidewall are not arranged on a side surface of the second region.

17. The semiconductor nanowire of claim 16 , wherein a thickness of the first sidewall and a thickness of the second sidewall one of increase and decrease in a direction extending toward the second region.

18. A semiconductor device with the semiconductor nanowire of claim 16 , the device comprising:

a source electrode connected to the first region of the semiconductor nanowire;

a drain electrode connected to the third region of the semiconductor nanowire;

a gate electrode facing the second region of the semiconductor nanowire; and

a gate insulating film arranged between the second region and the gate electrode.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 12, 2015
From: PANASONIC CORPORATION
To: JOLED INC
Reel/Frame 035187/0483 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 17, 2010
From: KAWASHIMA, TAKAHIRO; SAITOH, TOHRU
To: PANASONIC CORPORATION
Reel/Frame 023948/0384 →