Bus interface design apparatus and bus interface design method
A design method of a bus interface that includes an I/F interposed between chips, includes determining a bus width of the bus interface between chips and a type of the bus interface, based on a physical constraint condition between the chips, and automatically generating a bus IP core that comprises a circuit configured in accordance with the determined bus width and the bus interface.
1 . A design method of a bus interface that includes an I/F interposed between chips, comprising:
determining a bus width of the bus interface between chips and a type of the bus interface, based on a physical constraint condition between the chips; and
automatically generating a bus IP core that comprises a circuit configured in accordance with the determined bus width and the bus interface.
2 . The design method of the bus interface according to claim 1 , further comprising:
reading a bus interface design library in which a plurality of bus interface data of a chip-connecting bus are registered;
determining at least bus width and bus interface data based on the physical constraint conditions between chips;
automatically generating a bus IP core that comprises a circuit configured in accordance with the determined bus width and the bus interface data.
3 . The bus interface design method according to claim 1 , wherein
the bus interface includes one or more bus master modules, one or more bus slave modules, and a bus matrix unit for arbitrarily connecting at least one of the bus master modules and at least one of the bus slave modules.
4 . The bus interface design method according to claim 1 , wherein
the physical constraint condition includes at least one selected from a material of a print circuit board, a number of print circuit board layers, a wiring film thickness and a thickness between layers of the print circuit board, package information of an individual system LSI, a wiring distance between system LSIs, a wiring load model, and a maximum number of links allowed to be wired.
5 . The bus interface design method according to claim 2 , wherein
the logical constraint condition includes at least one selected from route information, which is path information indicating which master accesses which slave, a bus width and a bus clock frequency of an individual port.
6 . A bus interface design method comprising:
reading a logical constraint condition between chips and a physical constraint condition between the chips;
calculating a parameter required for a configuration of a bus interface; and
automatically generating the bus interface by performing the configuration of the bus interface.
7 . The bus interface design method according to claim 6 , wherein
the bus interface includes a transmitting and receiving circuit that drives a bus that connects the chips, and
the parameter is a property parameter of the transmitting and receiving circuit.
8 . The bus interface design method according to claim 6 , wherein
the bus interface includes a serial interface and/or a parallel interface that drives a bus that connects the chips, and
the parameter is a property parameter of the serial interface and/or the parallel interface.
9 . The bus interface design method according to claim 6 , wherein
the parameter is calculated by searching a database, which is configured to output the parameter, with use of the physical constraint condition as a key in a look-up table manner.
10 . The bus interface design method according to claim 6 , wherein
the property parameter is calculated by:
determining a number of master ports and a number of slave ports which are required for generating a bus matrix unit for arbitrarily connecting a plurality of bus master modules with a plurality of bus slave modules;
calculating a logical bandwidth required for an interface, which connects the chips, from the logical constraint condition; and
calculating a number of interfaces capable of realizing the logical bandwidth and the parameter of the transmitting and receiving circuit that drives each interface, from the physical constraint condition.
11 . The bus interface design method according to claim 7 , wherein
the property parameter includes at least one selected from a type of LVDS (Low Voltage Differential Signaling) buffer, an amount of deemphasis, an amount of preemphasis, and an amount of equalization in a receiving circuit.
12 . The bus interface design method according to claim 7 , wherein
the parameter of the configurable bus interface is stored in a bus interface design library,
the parameter includes at least one selected from a bus clock frequency, a number of master ports, a number of slave ports, a data bus width of each port, a start address and an end address of an address region for the case of slaves, a number of external interfaces, and a property parameter of a transmitting and receiving circuit of each external interface, and
an internal circuit configuration is reconfigured in accordance with the specified parameter.
13 . A bus interface design apparatus comprising:
a data readout unit that read out a bus interface design library and a physical constraint condition of chips, the bus interface design library being configured by registering a plurality of design purpose bus interfaces, each of the plurality of design purpose bus interfaces being for a bus that connects chips;
a determinator that determines a bus width and the design purpose bus interface based on the physical constraint condition; and
an executor that automatically generates a bus IP core that comprises a circuit configured in accordance with the determined bus width and the design purpose bus interface.
14 . The bus interface design apparatus according to claim 13 , further comprising:
a parameter calculator that calculates a parameter required for a configuration of the bus interface, wherein
the executor executes the configuration of the bus interface based on the parameter calculated by the parameter calculator.
15 . The bus interface design apparatus according to claim 14 , further comprising:
a transmitting and receiving circuit that drives the bus connecting semiconductor integrated circuits, wherein
the parameter is a property parameter of the transmitting and receiving circuit.
16 . The bus interface design apparatus according to claim 14 , wherein
the bus interface includes a serial interface and/or a parallel interface which drive the bus that connects semiconductor integrated circuits, and
the parameter is a property parameter of the serial interface and/or the parallel interface.
17 . The bus interface design apparatus according to claim 13 , wherein
the bus interface includes one or more bus master modules, one or more bus slave modules, and a bus matrix unit for arbitrarily connecting at least one of the bus master modules and at least one of the bus slave modules.
18 . The bus interface design apparatus according to claim 17 , wherein
the parameter calculator calculates the parameter by searching a database, which is configured to output the parameter, with use of the physical constraint condition as a key in a look-up table manner.
19 . The bus interface design apparatus according to claim 15 , wherein
the parameter calculator comprises:
a port number determinator that determines a number of master ports and a number of slave ports which are required for generating a bus matrix unit that is for arbitrarily connecting a plurality of bus master modules with a plurality of bus slave modules;
a bandwidth calculator that calculates a logical bandwidth from the logical constraint condition, the logical bandwidth being required for an interface that connects the semiconductor integrated circuits; and
a parameter output unit that calculates a number of interfaces capable of realizing the logical bandwidth and the parameter of the transmitting and receiving circuit that drives each interface, from the physical constraint condition.