Memory controller, system including the controller, and memory delay amount control method
View Patent ↗A memory controller transmits and receives data to and from a memory. The memory controller includes a delay control section deciding a set value indicative of a determined delay amount in response to a result of a comparison between a test data transmitted to the memory and test data received from the memory, and transmitting the decided set value to the memory, a taking-in section receiving the set value stored in the memory, and a delay adjustment section receiving data from the memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section.
1. A memory controller transmitting and receiving data to and from an external memory in an external region of a system large scale integration (LSI) including the memory controller, the memory controller comprising:
a delay control section including a delay holding section, coupled to an external terminal of the system LSI and deciding a set value indicative of a determined delay amount based on a result of a comparison between a test data transmitted to the external memory and test data received from the external memory to output the set value from the external terminal to the external memory in the external region of the system LSI;
a taking-in section receiving the set value in the external memory; and
a delay adjustment section receiving data from the external memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section,
wherein the set value is stored in both the delay holding section of the memory controller and the external memory in the external region of the system LSI including the memory controller.
2. The memory controller according to claim 1 , wherein the external memory comprises a dynamic random access memory (DRAM).
3. The memory controller according to claim 1 , wherein the data from the external memory comprises a clock, and wherein the delay adjustment section arranges a delay amount of a received clock in response to the set value received by the taking-in section.
4. The memory controller according to claim 1 , wherein the delay control section comprises:
a pattern generation section generating the test data; and
a command output section coupled to the delay holding section to read the set value from the delay holding section and to output the set value from the external terminal to the external memory, and transmitting a write command to store the test data and the set value to the memory.
5. The memory controller according to claim 4 , wherein the pattern generation section couples to an internal system including a central processing unit (CPU) and a read only memory (ROM), and generates the test data in response to a signal from the internal system.
6. The memory controller according to claim 4 , wherein the pattern generation section couples to an internal system including a central processing unit (CPU) and a nonvolatile memory, and generates the test data in response to a signal from the internal system.
7. The memory controller according to claim 1 , wherein the delay control section generates a plurality of test set values indicative of a test delay amount to receive the plurality of test data with a different delay amount from the external memory when the set value is decided, and
wherein the delay adjustment section arranges a delay amount of the plurality of test data returned from the external memory in response to the plurality of test set values.
8. The memory controller according to claim 7 , wherein the delay control section comprises:
a pattern comparison section comparing the plurality of test data with the different delay amounts returned from the external memory with the test data transmitted to the external memory.
9. The memory controller according to claim 1 , wherein the external memory is maintained with a power supply supplied when the memory controller operates in a power saving mode to be turned off.
10. A product comprising the memory controller according to claim 1 .
11. The memory controller according to claim 1 , wherein the external memory holds data in a self-refresh mode.
12. A system comprising:
an external memory in an external region of a system large scale integration (LSI);
a memory controller included in the system LSI and coupled to the external memory,
wherein the memory controller comprises:
a delay control section including a delay holding section coupled to an external terminal of the system LSI and deciding a set value indicative of a determined delay amount based on a result of a comparison between a test data transmitted to the memory and test data received from the external memory to output the set value from the external terminal to the external memory in the external region of the system LSI;
a taking-in section receiving the set value in the external memory; and
a delay adjustment section receiving data from the external memory, and arranging a delay amount of the received data in response to the set value received by the taking-in section,
wherein the set value is stored in both the delay holding section of the memory controller and the external memory in the external region of the system LSI including the memory controller.
13. The system according to claim 12 , further comprising:
an internal system coupled to the memory controller,
wherein the internal system comprises a central processing unit (CPU) and a read only memory (ROM), and
wherein the delay control section generates the test data in response to a signal from the internal system.
14. The system according to claim 12 , further comprising:
an internal system coupled to the memory controller,
wherein the internal system comprises a central processing unit (CPU) and a nonvolatile memory, and
wherein the delay control section generates the test data in response to a signal from the internal system.
15. The system according to claim 12 , wherein the external memory is maintained with power supply supplied when the memory controller operates in a power saving mode to be turned off.
16. The system according to claim 15 , wherein the memory controller receives the set value from the external memory when the memory controller returns from the power saving mode.
17. The system according to claim 12 , wherein the external memory comprises a dynamic random access memory (DRAM).
18. A memory delay amount control method for adjusting a delay amount in transmission and receiving of data to and from a memory, the memory delay amount control method comprising:
comparing test data transmitted to the memory with test data received from the memory;
deciding a set value indicative of a determined delay amount in response to a result of said comparing; and
storing the decided set value in the memory,
wherein the memory is maintained with power supply supplied when the memory controller operates in a power saving mode to be turned off.
19. The memory delay amount control method according to claim 18 , wherein the memory controller receives the set value from the memory when the memory controller returns from the power saving mode.
20. The memory delay amount control method according to claim 18 , wherein the memory comprises a dynamic random access memory (DRAM).