Operational trans-conductance amplifier with output clamp circuit
View Patent ↗An operational trans-conductance amplifier circuit having a voltage clamp circuit. The clamp circuit utilizes low area and power overhead, has a sharp clamp characteristic, and little degradation in the small-signal DC gain at the “knee” of the clamp characteristic. The clamp circuit includes a comparator circuit and a current control circuit. The amplifier and clamp circuits may further include a clamp voltage generator circuit.
1. A circuit comprising:
a folded cascode operational trans-conductance amplifier circuit, comprising:
a differential input stage;
a folded cascode circuit connected to the differential input stage; and
a current mirror circuit connected to the folded cascode circuit;
and
a clamp circuit connected to the trans-conductance amplifier circuit, the clamp circuit comprising:
a comparator circuit, comprising:
a first transistor connected to the folded cascode circuit; and
a second transistor connected between the first transistor and an output node;
and
a current control circuit connected to the comparator circuit, comprising:
a third transistor connected to the folded cased circuit, the output node and a node between the first and second transistors.
2. The circuit of claim 1 , wherein the current control circuit further comprises a fourth transistor connected to the third transistor and a node between the first and second transistors.
3. The circuit of claim 2 , wherein the first transistor provides a reference current to which the second transistor's current is compared.
4. The circuit of claim 3 , wherein the current control circuit sets a lower limit on an output voltage at an output node.
5. A circuit comprising:
a folded cascode operational trans-conductance amplifier circuit, comprising:
a differential input stage;
a folded cascode circuit connected to the differential input stage; and
a current mirror circuit connected to the folded cascode circuit;
and
a clamp circuit connected to the trans-conductance amplifier circuit, the clamp circuit comprising:
a comparator circuit, comprising:
a first transistor connected to an output node; and
a second transistor connected between the first transistor and the current mirror circuit;
and
a current control circuit connected to the comparator circuit, the current control circuit comprising:
a third transistor connected to the output node and a node on a left branch between the folded cascode circuit and the current mirror circuit.
6. The circuit of claim 5 , wherein the current control circuit further comprises a fourth transistor connected to the third transistor and a node between the first and second transistors.
7. The circuit of claim 1 , wherein the folded-cascode circuit comprises N-type MOSFETs, and the mirror cascode circuit comprises P-type MOSFETs.
8. A circuit comprising:
a pair of transistors forming a differential input stage;
a first set of four transistors forming a folded cascode circuit, wherein one transistor of the pair of differential input stage transistors is connected to a first node of the folded cascode circuit, and a second transistor of the pair of differential input stage transistors is connected to a second node of the folded cascode circuit;
a current mirror circuit connected to the folded cascode circuit; and
a clamp circuit, the clamp circuit comprising:
a first comparator transistor having a source connected to the second node of the folded cascode circuit, and a gate connected to a biasing node in the folded cascode circuit;
a second comparator transistor having a drain connected to a drain of the first comparator transistor, a gate connected to a clamp voltage, and a source connected to an output node; and
a third transistor having a source connected to the first node of the folded cascode circuit, a drain connected to the output node, and a gate connected to the drain of the second comparator transistor.
9. The circuit of claim 8 , wherein the clamp circuit further comprises a fourth transistor having a source connected to the source of the third transistor, and a drain and gate connected to the gate of the third transistor and the drain of the second comparator transistor.
10. The circuit of claim 9 , further comprising a transistor connected to the sources of the differential input pair of transistors.
11. The circuit of claim 10 , further comprising a clamp voltage generator circuit connected to the gate of the second comparator transistor.
12. The circuit of claim 11 , wherein the clamp voltage generator circuit comprises:
a first clamp generator transistor having a source connected to the first node of the folded cascode circuit; and
a second clamp generator transistor having a drain and gate connected to the gate of the second comparator transistor, and a source connected to a node of a transistor in the current mirror circuit.
13. The circuit of claim 11 , wherein the clamp voltage generator circuit comprises:
a first clamp generator transistor having a source connected to the first node of the folded cascode circuit; and
a second clamp generator transistor having a drain and gate connected to the gate of the second comparator transistor, and a source connected to a third node of a transistor in the mirror cascode circuit.
14. The circuit of claim 11 , wherein the clamp voltage generator circuit comprises:
a first clamp generator transistor having a source connected to the first node of the folded cascode circuit; and
a second clamp generator transistor having a drain and gate connected to the gate of the second comparator transistor, and a source connected to an external control voltage.
15. A circuit comprising:
a folded cascode operational trans-conductance amplifier circuit, comprising:
a differential input stage;
a folded cascode circuit connected to the differential input stage; and
a mirror cascode circuit connected to the folded cascode circuit;
and
a clamp circuit connected to the trans-conductance amplifier circuit, the clamp circuit comprising:
a comparator circuit comprising:
a first transistor connected to the mirror cascode circuit; and
a second transistor connected to the first transistor and an output node, the output node connected to a second branch connecting the folded cascode circuit and the mirror cascode circuit;
and
a current control circuit comprising:
a third transistor connected to the output node, and a node of a first branch connecting the folded cascode circuit and the mirror cascode circuit.
16. The circuit of claim 15 , wherein the current control circuit further comprises a fourth transistor connected to the third transistor and a node between the first and second transistors.
17. The circuit of claim 15 , further comprising a clamp voltage generator circuit connected to the gate of the second comparator transistor.
18. The circuit of claim 15 , wherein the clamp voltage generator circuit comprises:
a first clamp generator transistor having a gate and drain connected to the gate of the second comparator transistor and a source connected to a control voltage; and
a second clamp generator transistor having a drain connected to the gate and drain of the first clamp generator transistor, a source connected to the mirror cascode circuit, and a gate connected to a bias voltage.
19. A circuit comprising:
a signal input stage, comprising:
a differential input stage; and
a mirror cascode circuit connected to the differential input stage;
and
a clamp circuit connected to input stage and mirror cascode circuit, the clamp circuit comprising:
a comparator circuit comprising:
a first transistor connected to the mirror cascode circuit; and
a second transistor connected to the first transistor and an output node, the output node connected to a second branch connecting the input stage and the mirror cascode circuit;
and
a current control circuit comprising:
a third transistor connected to the output node, and a node of a first branch connecting the input stage and the mirror cascode circuit.
20. The circuit of claim 19 , further comprising a fourth transistor connected to the third transistor and a node between the first and second transistors.
21. A circuit comprising:
a pair of transistors forming a differential input stage;
a first set of four transistors forming a folded cascode circuit, wherein one transistor of the pair of differential input stage transistors is connected to a first node of the folded cascode circuit, and a second transistor of the pair of differential input stage transistors is connected to a second node of the of folded cascode circuit;
a second set of four transistors forming a mirror cascode circuit connected to the folded cascode circuit; and
a clamp circuit, the clamp circuit comprising:
a first comparator transistor having a source connected to the output node, and a gate connected to a clamp voltage;
a second comparator transistor having a drain connected to a drain of the first comparator transistor, a gate connected to a biasing voltage, and a source connected to a node in the mirror cascode circuit; and
a third transistor having a drain connected to the output node, and a source to a node of one branch connecting the folded cascode circuit and the mirror cascode circuit.
22. The circuit of claim 21 , wherein the clamp circuit further comprises a fourth transistor having a drain and gate connected to a drain of the first comparator transistor, and a source connected to a source of the third transistor.
23. The circuit of claim 21 , further comprising a clamp voltage generator circuit connected to the gate of the second comparator transistor.
24. The circuit of claim 23 , wherein the clamp voltage generator circuit comprises:
a first clamp generator transistor having a gate and drain connected to the gate of the second comparator transistor and a source connected to a control voltage; and
a second clamp generator transistor having a drain connected to the gate and drain of the first clamp generator transistor, a source connected to the mirror cascode circuit, and a gate connected to a bias voltage.