Rare earth enhanced high electron mobility transistor and method for fabricating same
View Patent ↗According to one embodiment, a high electron mobility transistor (HEMT) comprises an insulator layer comprising a first group III-V intrinsic layer doped with a rare earth additive. The HEMT also comprises a second group III-V intrinsic layer formed over the insulator layer, and a group III-V semiconductor layer formed over the second group III-V intrinsic layer. In one embodiment, a method for fabricating a HEMT comprises forming a first group III-V intrinsic layer and doping the first group III-V intrinsic layer with a rare earth additive to produce an insulator layer. The method also comprises forming a second group III-V intrinsic layer over the insulator layer, and further forming a group III-V semiconductor layer over the second group III-V intrinsic layer. A two-dimensional electron gas (2DEG) is formed at a heterojunction interface of the group III-V semiconductor layer and the second group III-V intrinsic layer.
1. A high electron mobility transistor (HEMT) comprising:
a first group III-V intrinsic layer;
a second group III-V intrinsic layer formed over said first group III-V intrinsic layer;
a group III-V semiconductor layer formed over said second group III-V intrinsic layer, said group III-V semiconductor layer and said second group III-V intrinsic layer forming a heterojunction for generating a two-dimensional electron gas (2DEG);
said first group III-V intrinsic layer doped with a rare earth additive, thereby producing an insulator layer reducing leakage of charge carriers from said 2DEG.
2. The HEMT of claim 1 , wherein said first group III-V intrinsic layer is formed utilizing a technique selected from the group consisting of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and hydride vapor phase epitaxy (HVPE).
3. The HEMT of claim 1 , wherein said group III-V semiconductor layer comprises a group III-V ternary semiconductor.
4. The HEMT of claim 1 , wherein said group III-V semiconductor layer comprises aluminum gallium nitride (AlGaN).
5. The HEMT of claim 1 , wherein said second group III-V intrinsic layer comprises a group III-V binary semiconductor.
6. The HEMT of claim 1 , wherein said second group III-V intrinsic layer comprises gallium nitride (GaN).
7. The HEMT of claim 1 , wherein said insulator layer comprises said rare earth additive at a concentration greater than 0.0 atomic percent and less than or equal to 1.0 atomic percent.
8. The HEMT of claim 1 , wherein said rare earth additive comprises a lanthanide of atomic number fifty-eight or greater.
9. The HEMT of claim 1 , wherein said rare earth additive comprises a lanthanide selected from the group consisting of cerium (Ce), praseodymium (Pr), europium (Eu), erbium (Er), and thulium (Tm).
10. A method for fabricating a high electron mobility transistor (HEMT), the method comprising:
forming a first group III-V intrinsic layer;
doping said first group III-V intrinsic layer with a rare earth additive to produce an insulator layer;
forming a second group III-V intrinsic layer over said insulator layer;
forming a group III-V semiconductor layer over said second group III-V intrinsic layer, said group III-V semiconductor layer and said second group III-V intrinsic layer forming a hetero unction for generating a two-dimensional electron gas (2DEG);
said insulator layer reducing leakage of charge carriers from said 2DEG.
11. The method of claim 10 , wherein forming said first group III-V intrinsic layer is performed utilizing a technique selected from the group consisting of molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and hydride vapor phase epitaxy (HVPE).
12. The method of claim 10 , wherein said group semiconductor layer comprises a group III-V ternary semiconductor.
13. The method of claim 10 , wherein said group III-V semiconductor layer comprises aluminum gallium nitride (AlGaN).
14. The method of claim 10 , wherein said second group III-V intrinsic layer comprises a group III-V binary semiconductor.
15. The method of claim 10 , wherein said second group III-V intrinsic layer comprises gallium nitride (GaN).
16. The method of claim 10 , wherein doping said first group III-V intrinsic layer comprises doping with said rare earth additive to a concentration greater than 0.0 atomic percent and less than or equal to 1.0 atomic percent.
17. The method of claim 10 , wherein said rare earth additive comprises a lanthanide of atomic number fifty-eight or greater.
18. The method of claim 10 , wherein said rare earth additive comprises a lanthanide selected from the group consisting of cerium (Ce), praseodymium (Pr), europium (Eu), erbium (Er), and thulium (Tm).