Tri-core architecture for reducing MAC layer processing latency in base stations
View Patent ↗A tri-core architecture for reducing MAC layer processing latency at the base stations is described. The new architecture minimizes the processing delay by introducing a pipelined approach. The fundamental concept involves splitting the Medium Access Control (MAC) layer functionality into three distinct tasks, with each processor performing a given task. All tasks will be thus performed concurrently, avoiding much of the overhead encountered while processing received packets and preparing packets to be transmitted.
1. A processing system that minimizes the latency associated with medium access control protocol layer processing for a medium access control protocol that combines contention-free and contention-based medium access control protocols into a heterogeneous medium access control protocol used for forwarding Internet Protocol packets containing voice traffic, signaling traffic, and application data traffic between a base station and mobile nodes in a voice over internet protocol system on a wireless network comprising:
A base station in electrical communication with the Internet;
one or more mobile nodes in wireless electrical communication with said base station;
said base station and said one or more mobile nodes each having a medium access control protocol;
said medium access control protocol having super-frames of equal intervals of time;
each of said super-frames made up of an initial time for contention-free timeslot based access voice traffic and a remainder time for contention-based access signaling traffic and application data traffic;
said base station capable of dynamically determining a time duration of said super-frames and said initial time for contention-free timeslot based access based on a packetization interval determined by the duration of the voice traffic in said Internet Protocol packets; and,
said base station having three concurrently running processors comprised of an Ethernet processor which acts as the interface to the Internet, a medium access control processor that processes tasks associated with Internet Protocol packets, and an air interface processor which acts as the interface to wireless links.
2. The processing system of claim 1 wherein said Ethernet processor runs asynchronously, alternating between receiving packets from the Internet and transmitting packets to the Internet.