Level shift circuit and power semiconductor device

1. A level shift circuit connectable to a power semiconductor device including a high-side NMOS transistor serving as a high-side switching element, a low-side switching element, and a bootstrap circuit that generate a first potential by shifting a source potential of the high-side NMOS transistor to high potential side, the level shift circuit comprising:

a drive transistor having a source-drain path coupled between the first potential and the source potential, to generate an output signal for driving a gate of the high-side NMOS transistor;

a first PMOS transistor having a source and a back gate coupled to the first potential, and a drain coupled to a gate of the drive transistor;

a first clamp transistor of PMOS type having a gate coupled to the source potential of the high-side NMOS transistor, and a source and a back gate coupled to the drain of the first PMOS transistor; and

a second clamp transistor of PMOS type having a gate coupled to the source potential of the high-side NMOS transistor, and a source and a back gate coupled to a gate of the first PMOS transistor.

2. The level shift circuit according to claim 1 , further comprising:

a first NMOS transistor having a source and a back gate coupled to a ground potential, and a gate supplied with a pulse width modulation (PWM) control signal;

a second NMOS transistor having a source and a back gate coupled to the ground potential, and a gate supplied with an inverted signal of the PWM control signal; and

a second PMOS transistor having a source and a back gate coupled to the first potential, and a drain coupled to each of the gate of the first PMOS transistor and the source of the second clamp transistor,

wherein the first clamp transistor has a source-drain path coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, and

the second clamp transistor has a source-drain path coupled between the drain of the second PMOS transistor and a drain of the second NMOS transistor.

3. The level shift circuit according to claim 2 , further comprising:

a third clamp transistor of PMOS type and a fourth clamp transistor of NMOS type connected in series between a drain of the first clamp transistor and the drain of the first NMOS transistor; and

a fifth clamp transistor of PMOS type and a sixth clamp transistor of NMOS type connected in series between a drain of the second clamp transistor and the drain of the second NMOS transistor,

wherein the third and fifth clamp transistors each have a gate coupled to the ground potential, and

the fourth and sixth clamp transistors each have a gate coupled to the power supply potential.

4. The level shift circuit according to claim 3 , wherein

a source and a back gate of the third clamp transistor are coupled to the drain of the first clamp transistor,

a drain of the third clamp transistor is coupled to a drain of the fourth clamp transistor,

a source and a back gate of the fourth clamp transistor are coupled to the drain of the first NMOS transistor,

a source and a back gate of the fifth clamp transistor are coupled to the drain of the second clamp transistor;

a drain of the fifth clamp transistor is coupled to a drain of the sixth clamp transistor, and

a source and a back gate of the sixth clamp transistor are coupled to the drain of the second NMOS transistor.

5. The level shift circuit according to claim 2 , further comprising:

a third PMOS transistor having a source coupled to the first potential, and a gate coupled to the drain of the second PMOS transistor;

a third NMOS transistor having a source coupled to a source of the high-side NMOS transistor, a drain coupled to a drain of the drive transistor, and a gate coupled to a drain of the third PMOS transistor; and

a fourth NMOS transistor having a source coupled to the source of the high-side NMOS transistor, a drain coupled to the drain of the third PMOS transistor, and a gate coupled to the drain of the drive transistor.

6. A level shift circuit connectable to a power semiconductor device including a high-side NMOS transistor serving as a high-side switching element, a low-side switching element, and a bootstrap circuit that generate a first potential by shifting a source potential of the high-side NMOS transistor to high potential side, the level shift circuit comprising:

a drive transistor having a source-drain path coupled between the first potential and the source potential, to generate an output signal for driving a gate of the high-side NMOS transistor;

a first PMOS transistor having a source and a back gate coupled to the first potential, and a drain coupled to a gate of the drive transistor; and

a clamp circuit supplied with the source potential of the high-side NMOS transistor as a bias voltage, to clamp a gate potential and a drain potential of the first PMOS transistor to the source potential of the high-side NMOS transistor or higher.

7. A power semiconductor device comprising:

a high-side NMOS transistor serving as a high-side switching element;

a low-side switching element coupled to the high-side NMOS transistor,

a bootstrap circuit that shifts a level of a source potential of the high-side NMOS transistor to a high potential side to generate a first potential;

a drive transistor having a source-drain path coupled between the first potential and the source potential, to generate an output signal for driving a gate of the high-side NMOS transistor;

a first PMOS transistor having a source and a back gate coupled to the first potential, and a drain coupled to a gate of the drive transistor;

a first clamp transistor of PMOS type having a gate coupled to the source potential of the high-side NMOS transistor, and a source and a back gate coupled to the drain of the first PMOS transistor; and

a second clamp transistor of PMOS type having a gate coupled to the source potential of the high-side NMOS transistor, and a source and a back gate coupled to a gate of the first PMOS transistor.

8. The power semiconductor device according to claim 7 , further comprising:

a first NMOS transistor having a source and a back gate coupled to a ground potential, and a gate supplied with a pulse width modulation (PWM) control signal;

a second NMOS transistor having a source and a back gate coupled to the ground potential, and a gate supplied with an inverted signal of the PWM control signal; and

a second PMOS transistor having a source and a back gate coupled to the first potential, and a drain coupled to each of the gate of the first PMOS transistor and the source of the second clamp transistor,

wherein the first clamp transistor has a source-drain path coupled between the drain of the first PMOS transistor and a drain of the first NMOS transistor, and

the second clamp transistor has a source-drain path coupled between the drain of the second PMOS transistor and a drain of the second NMOS transistor.

9. The power semiconductor device according to claim 8 , further comprising:

a third clamp transistor of PMOS type and a fourth clamp transistor of NMOS type connected in series between a drain of the first clamp transistor and the drain of the first NMOS transistor; and

a fifth clamp transistor of PMOS type and a sixth clamp transistor of NMOS type connected in series between a drain of the second clamp transistor and the drain of the second NMOS transistor,

wherein the third and fifth clamp transistors each have a gate coupled to the ground potential, and

the fourth and sixth clamp transistors each have a gate coupled to the power supply potential.

10. The power semiconductor device according to claim 9 , wherein

a source and a back gate of the third clamp transistor are coupled to the drain of the first clamp transistor,

a drain of the third clamp transistor is coupled to a drain of the fourth clamp transistor,

a source and a back gate of the fourth clamp transistor are coupled to the drain of the first NMOS transistor,

a source and a back gate of the fifth clamp transistor are coupled to the drain of the second clamp transistor;

a drain of the fifth clamp transistor is coupled to a drain of the sixth clamp transistor, and

a source and a back gate of the sixth clamp transistor are coupled to the drain of the second NMOS transistor.

11. The power semiconductor device according to claim 8 , further comprising:

a third PMOS transistor having a source coupled to the first potential, and a gate coupled to the drain of the second PMOS transistor;

a third NMOS transistor having a source coupled to a source of the high-side NMOS transistor, a drain coupled to a drain of the drive transistor, and a gate coupled to a drain of the third PMOS transistor; and

a fourth NMOS transistor having a source coupled to the source of the high-side NMOS transistor, a drain coupled to the drain of the third PMOS transistor, and a gate coupled to the drain of the drive transistor.

12. A level shift circuit supplied with a first control signal and a second control signal having a voltage value shifted from a voltage value of the first control signal to a high potential side by a predetermined potential, and receiving a first drive control signal, the level shift circuit comprising:

a drive transistor that outputs a second drive control signal obtained by shifting a voltage level of the first drive control signal;

a first transistor supplied with the second control signal for level shifting and controlled based on the first drive control signal;

a second transistor receiving the first drive control signal; and

a clamp transistor inserted between the first transistor and the second transistor and having a gate applied with the first control signal, to clamp a drain potential of the first transistor.