Circuit device

1. A circuit device comprising:

a first transmitting inductor constituted essentially of a first helical conductive pattern, and which receives an input of a transmitted signal;

a first insulating layer provided over or under said first transmitting inductor;

a first receiving inductor, located in a region overlapping with said first transmitting inductor through said first insulating layer and constituted essentially of a second helical conductive pattern, and which generates a received signal corresponding to said transmitted signal; and

a second receiving inductor, connected in series to said first receiving inductor and constituted essentially of a third helical conductive pattern, and which generates a voltage in an opposite direction to that generated by said first receiving inductor, in response to a magnetic field of the same direction.

2. The circuit device according to claim 1 ,

wherein said first receiving inductor and said second receiving inductor are wound in the same direction, and respective inner end portions or respective outer end portions are electrically connected to each other.

3. The circuit device according to claim 1 ,

wherein said first receiving inductor and said second receiving inductor are wound in opposite directions, and said inner end portion of said first receiving inductor and said outer end portion of said second receiving inductor, or said outer end portion of said first receiving inductor and said inner end portion of said second receiving inductor are electrically connected.

4. The circuit device according to claim 1 , further comprising:

a second transmitting inductor provided in a region overlapping with said second receiving inductor through said second insulating layer or said first insulating layer, and constituted essentially of a fourth helical conductive pattern;

wherein said second transmitting inductor receives the same transmitted signal as that received by said first transmitting inductor; and

said first transmitting inductor and said second transmitting inductor generate a magnetic field in opposite directions, upon receiving said transmitted signal.

5. The circuit device according to claim 4 ,

wherein said first transmitting inductor and said second transmitting inductor are wound in opposite directions;

said inner end portion of said first transmitting inductor and said outer end portion of said second transmitting inductor are electrically connected; and

said outer end portion of said first transmitting inductor and said inner end portion of said second transmitting inductor are electrically connected.

6. The circuit device according to claim 4 ,

wherein said second transmitting inductor is wound in the same direction as said first transmitting inductor, and the respective inner end portions, as well as the respective outer end portions are electrically connected.

7. The circuit device according to claim 4 ,

wherein no other inductor is provided between said first transmitting inductor and said second transmitting inductor.

8. The circuit device according to claim 1 , further comprising:

a third receiving inductor located in a region overlapping with said second receiving inductor through a third insulating layer or said first insulating layer, and constituted essentially of a fifth helical conductive pattern.

9. The circuit device according to claim 8 ,

wherein said inner end portion of said first receiving inductor is electrically connected to said inner end portion of said second receiving inductor; and

said outer end portion of said first receiving inductor is electrically connected to said outer end portion of said second receiving inductor.

10. The circuit device according to claim 8 , comprising:

an even number of signal transmitting circuits including said first transmitting inductor, said first receiving inductor, said second receiving inductor, and said third receiving inductor;

wherein said even number of signal transmitting circuits are disposed such that the same inductors are located adjacent to each other, and the same transmitted signal is input in common to said first transmitting inductors;

said first transmitting inductors adjacently disposed generate a magnetic field in opposite directions upon receipt of said transmitted signal; and

said third receiving inductors adjacently disposed generate a voltage in opposite directions in response to said magnetic field of the same direction, and are connected in series to each other in such a direction that said voltage generated in said third receiving inductor is summed when said transmitted signal is input to said first transmitting inductor.

11. The circuit device according to claim 8 , comprising:

a substrate;

a first transistor formed on said substrate so as to constitute one of a transmitting circuit that inputs said transmitted signal to said first transmitting inductor and a receiving circuit that receives said received signal from said first receiving inductor;

wherein said first transmitting inductor, said first receiving inductor, said second receiving inductor, and said third receiving inductor are provided over said substrate;

in the case where said first transistor constitutes said transmitting circuit said first transmitting inductor is located below said first receiving inductor; and

in the case where said first transistor constitutes said receiving circuit said third receiving inductor is located below said second receiving inductor.

12. The circuit device according to claim 8 , comprising:

a first substrate and a second substrate;

said first transmitting inductor and said first receiving inductor are provided over said first substrate, and said second receiving inductor and said third receiving inductor are provided over said second substrate.

13. The circuit device according to claim 1 ,

wherein said first insulating layer includes at least a first interconnect layer, and a second interconnect layer located closer to said first receiving inductor than said first interconnect layer is;

an inner end portion of said first transmitting inductor does not overlap in a plan view with an inner end portion of said first receiving inductor;

said circuit device comprising a first escape routing formed in said first interconnect layer so as to lead out said inner end portion of said first transmitting inductor to outside of said first transmitting inductor in a plan view; and

a second escape routing formed in said second interconnect layer so as to lead out said inner end portion of said first receiving inductor to outside of said first receiving inductor in a plan view;

said first escape routing and said second escape routing being disposed not to overlap.

14. The circuit device according to claim 1 , further comprising:

a cover layer provided over one of said first transmitting inductor and said first receiving inductor located at an upper position than the other;

an opening formed on said cover layer and in which said inner end portion of said upper inductor is exposed toward outside of said cover layer; and

a wire connected to said inner end portion of said upper inductor, so as to lead out said inner end portion to outside of said upper inductor in a plan view.

15. The circuit device according to claim 1 ,

wherein said first conductive pattern constituting said first transmitting inductor and said second conductive pattern constituting said first receiving inductor do not overlap in a plan view.

16. The circuit device according to claim 1 , comprising:

a silicon-on-insulator (SOI) substrate; and

a plurality of embedded insulating layers formed in a silicon layer of said SOI substrate with a spacing from each other;

wherein said first transmitting inductor and said first receiving inductor are located over said plurality of embedded insulating layers in said SOI substrate.