Image display device
View Patent ↗Disclosed herein is an image display device including a display section formed by arranging pixel circuits in a matrix form. Each pixel circuit includes at least a light emitting element, a drive transistor, a holding capacitor, and a write transistor. A light emission and non-light emission periods are alternately repeated. A light emission period start voltage and a non-light emission period start voltage are alternately output to the signal line. The terminal voltage of the holding capacitor is set to start the light emission and non-light emission periods. The write signal is set to sequentially delay the timings. The power drive signal is set in units of a plurality of successive lines. The drain voltage of the drive transistor is pulled up to high level at a time other than when the one of the terminals is connected to the signal line by the write signal in different lines.
1. An image display device comprising:
a display section formed by arranging pixel circuits in a matrix form, each of the pixel circuits including at least:
a light emitting element;
a drive transistor adapted to current-drive the light-emitting element with a drive current commensurate with a gate-to-source voltage in response to a power drive signal applied to a drain of the drive transistor via a power scan line;
a holding capacitor adapted to hold the gate-to-source voltage; and
a write transistor adapted to be controlled by a write signal supplied via a write signal scan line to connect a terminal of the holding capacitor to a signal line so as to set a terminal voltage of the holding capacitor to a signal line voltage;
wherein:
a light emission period during which the light-emitting element emits light, and non-light emission period during which the light-emitting element does not emit light, are alternately repeated;
a light emission period start voltage adapted to at least start the light emission period, and a non-light emission period start voltage adapted to start the non-light emission period, are alternately output to the signal line;
the terminal voltage of the holding capacitor is set by controlling the write transistor using the write signal so as to start the light emission period and the non-light emission period;
the write signal is set in such a manner as to sequentially delay timings at which to set the light emission period start voltage between successive lines;
the power drive signal is commonly set in units of the successive lines; and
a drain voltage of the drive transistor is pulled up to high level using the power drive signal at a time other than when the terminal of the holding capacitor is connected to the signal line by the write signal in the pixel circuits in different lines.
2. The image display device according to claim 1 , wherein
in the pixel circuit, the gate-to-source voltage is set to a level equal to or greater than the threshold voltage of the drive transistor by controlling the write transistor with the write signal, and next, the gate-to-source voltage is set is set to a level commensurate with the threshold voltage of the drive transistor; and
then, the terminal voltage of the holding capacitor is set to the signal line voltage to initiate the light emission period.
3. The image display device according to claim 2 , wherein
a correction voltage adapted to correct the variation in the threshold voltage of the drive transistor is further output to the signal line; and
the gate-to-source voltage is set to a voltage level equal to or greater than the threshold voltage of the drive transistor by pulling the drain voltage of the drive transistor to low level with the power drive signal and by setting the terminal voltage of the holding capacitor to the correction voltage by controlling the write transistor with the write signal.
4. The image display device according to claim 1 , wherein
the power drive signal is pulled up to high level when the signal line voltage is pulled down to low level.
5. An image display device comprising:
display means formed by arranging pixel circuits in a matrix form, each of the pixel circuits including at least:
a light emitting element;
a drive transistor adapted to current-drive the light-emitting element with a drive current commensurate with a gate-to-source voltage in response to a power drive signal applied to a drain of the drive transistor via a power scan line;
a holding capacitor adapted to hold the gate-to-source voltage; and
a write transistor adapted to be controlled by a write signal supplied via a write signal scan line to connect a terminal of the holding capacitor to a signal line so as to set a terminal voltage of the holding capacitor to a signal line voltage;
wherein:
a light emission period during which the light-emitting element emits light, and non-light emission period during which the light-emitting element does not emit light, are alternately repeated;
a light emission period start voltage adapted to at least start the light emission period, and a non-light emission period start voltage adapted to start the non-light emission period, are alternately output to the signal line;
the terminal voltage of the holding capacitor is set by controlling the write transistor using the write signal so as to start the light emission period and the non-light emission period;
the write signal is set in such a manner as to sequentially delay timings at which to set the light emission period start voltage between successive lines;
the power drive signal is commonly set in units of the successive lines; and
a drain voltage of the drive transistor is pulled up to high level using the power drive signal at a time other than when the terminal of the holding capacitor is connected to the signal line by the write signal in the pixel circuits in different lines.