Semiconductor integrated circuit and method of testing the same

1. A semiconductor integrated circuit comprising:

a first path that includes a first logic circuit;

a second path that includes a second logic circuit; and

a subsequent-stage circuit that is connected to an output of the first path and is connected to an output of the second path,

wherein the second path further comprises:

a first internal path that is selected as a propagation path during a normal operation period; and

a second internal path that is selected as a propagation path during a test operation period and includes a delay circuit having a delay amount larger than a delay amount of the first internal path.

2. The semiconductor integrated circuit according to claim 1 , further comprising:

a first switch that is provided in the first internal path; and

a second switch that is provided in the second internal path,

wherein control signals complementary to each other between the normal operation period and the test operation period are supplied to the first switch and the second switch.

3. The semiconductor integrated circuit according to claim 1 , further comprising a clock generation circuit that generates a clock to be input to the first logic circuit and the second logic circuit at substantially the same timing.

4. The semiconductor integrated circuit according to claim 1 , wherein

an output of the first logic circuit is directly connected to the subsequent-stage circuit, and

an output of the second logic circuit is connected to the subsequent-stage circuit through one of the first internal path and the second internal path.

5. The semiconductor integrated circuit according to claim 1 , wherein

the first logic circuit supplies a plurality of signals to the subsequent-stage circuit, and

the subsequent-stage circuit selects and outputs at least one of the plurality of signals supplied from the first logic circuit in accordance with an output of the second logic circuit.

6. The semiconductor integrated circuit according to claim 1 , wherein the first internal path is connected in parallel with the second internal path.

7. A test method comprising:

adding a delay larger than a delay that is caused during a normal operation period, to one of first and second paths that have logic circuits respectively, based on which output thereof is connected to a subsequent-stage circuit earlier;

testing an operation of a semiconductor integrated circuit including the first path, the second path, and the subsequent-stage circuit.

8. The test method according to claim 7 , wherein, in a path selected to be added the delay, a first internal path selected as a propagation path during the normal operation period and a second internal path selected as a propagation path during the test operation period are connected in parallel.

9. The test method according to claim 8 , wherein

the first internal path is provided with a first switch,

the second internal path is provided with a second switch, and wherein

control signals complementary to each other between the normal operation period and the test operation period are supplied to the first switch and the second switch.

10. The test method according to claim 8 , wherein the second internal path is incorporated in the semiconductor integrated circuit.

11. The test method according to claim 7 , wherein the logic circuits respectively included in the first and second paths operate based on clocks input at substantially the same timing.