High dielectric constant gate oxides for a laterally diffused metal oxide semiconductor (LDMOS)
An apparatus is disclosed to increase a breakdown voltage of a semiconductor device. The semiconductor device includes a first heavily doped region to represent a source region. A second heavily doped region represents a drain region of the semiconductor device. A metal region represents a gate region of the semiconductor device. The semiconductor device includes a gate oxide positioned between the source region and the drain region, below the gate region. The semiconductor device uses a high dielectric constant (high-κ dielectric) material.
1 . A semiconductor device, comprising:
a first region formed within a semiconductor substrate forming a source region;
a second region formed within the semiconductor substrate forming a drain region;
a metal region positioned between the source region and the drain region forming a gate region;
a gate oxide region formed with a high dielectric constant (high-κ dielectric) material in contact with the gate region; and
a shallow trench isolation (STI) region, positioned in between the source region and the drain region, formed within the semiconductor substrate using a dielectric material.
2 . The semiconductor device of claim 1 , wherein the gate region is formed using at least one of a group consisting of: TiN, TaSiN, WN, TaN, and TaCx.
3 . The semiconductor device of claim 1 wherein the high-κ dielectric material includes at least one of a group consisting of: hafnium silicate, zirconium silicate, hafnium dioxide and zirconium dioxide.
4 . The semiconductor device of claim 1 , wherein the high-κ dielectric material has a dielectric constant greater than a dielectric constant of SiO 2 .
5 . The semiconductor device of claim 1 , wherein the high-κ dielectric material has a dielectric constant between 10 and 30.
6 . The semiconductor device of claim 1 , wherein the source region and the drain region are implanted with n-type material.
7 . The semiconductor device of claim 1 , wherein the source region and the drain region are implanted with p-type material.
8 . The semiconductor device of claim 1 , further comprising:
a well implanted onto the semiconductor substrate, the well including a first side positioned between the source region and the drain region.
9 . The semiconductor device of claim 8 , wherein the well is implanted with n-type material.
10 . The semiconductor device of claim 8 , wherein the well is implanted with p-type material.
11 . (canceled)
12 . The semiconductor device of claim 1 , wherein the STI region includes a first side substantially vertically aligned with a first side of the gate region and a second side adjacent to a first side of the drain region.
13 . The semiconductor device of claim 12 , wherein the second side of the STI region is in substantial contact with the first side of the drain region.
14 . The semiconductor device of claim 1 , wherein the LDMOS device is formed using a logic foundry technology having a low operating voltage process and a high operating voltage process, and wherein a thickness of the gate oxide region is approximately equal to a thickness of a thin gate oxide of the low operating voltage process.
15 . The semiconductor device of claim 14 , wherein the thickness of the gate oxide region is approximately 20 angstrom (Å).
16 . The semiconductor device of claim 1 , wherein the drain region is displaced from the gate region by a substantially horizontal distance.
17 . The semiconductor device of claim 1 , further comprising:
a spacer formed onto the semiconductor substrate in between the drain region and the gate region, the drain region being displaced from the spacer by a substantially horizontal distance.
18 . The semiconductor device of claim 17 , wherein the spacer is formed using a dielectric material.
19 . A semiconductor device, comprising:
a first region formed within a semiconductor substrate forming a source region;
a second region formed within the semiconductor substrate forming a drain region;
a metal region positioned between the source region and the drain region forming a gate region, the drain region being displaced from the gate region by a first substantially horizontal distance;
a gate oxide region formed with a high dielectric constant (high-κ dielectric) material in contact with the gate region; and
a shallow trench isolation (STI) region, positioned in between the source region and the drain region, the STI region being displaced from the gate region by a second substantially horizontal distance.