Thin film transistor, method of fabricating the same, and organic light emitting diode display device including the same
View Patent ↗A thin film transistor (TFT), including a crystalline semiconductor pattern on a substrate, a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein, a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes, an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein, and source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes.
1. A thin film transistor (TFT), comprising:
a buffer layer on a substrate;
a crystalline semiconductor pattern on the buffer layer;
a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein;
a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes;
an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein; and
source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes, wherein:
the semiconductor pattern access hole partially exposes the crystalline semiconductor pattern, and
the exposed crystalline semiconductor pattern is in contact with the interlayer insulating layer through the semiconductor pattern access hole.
2. The TFT as claimed in claim 1 , wherein:
the semiconductor pattern access hole is spaced apart from the first source/drain contact holes,
the semiconductor pattern access hole is at an upper region of the semiconductor pattern, and
the semiconductor pattern access hole corresponds to a region other than a channel region of the semiconductor pattern.
3. The TFT as claimed in claim 1 , wherein the gate electrode has a thickness of about 50 nm to about 200 nm.
4. The TFT as claimed in claim 1 , wherein the gate electrode is formed of aluminum, chromium, molybdenum, or a combination thereof.
5. The TFT as claimed in claim 1 , wherein the gate insulating layer includes two or more semiconductor pattern access holes therein.
6. The TFT as claimed in claim 1 , wherein the interlayer insulating layer is in contact with an upper surface of the exposed crystalline semiconductor pattern, the interlayer insulating layer being in the semiconductor pattern access hole.
7. The TFT as claimed in claim 6 , wherein the interlayer insulating layer directly contacts the gate electrode and the gate insulating layer is between the interlayer insulating layer and the crystalline semiconductor pattern in an area surrounding the semiconductor pattern access hole.
8. The TFT as claimed in claim 6 , wherein the interlayer insulating layer fills the semiconductor pattern access hole.
9. An organic light emitting diode (OLED) display device, comprising:
OLEDs configured to emit light; and
thin film transistors (TFTs) coupled to the OLEDs, each TFT including:
a buffer layer on a substrate;
a crystalline semiconductor pattern on the buffer layer;
a gate insulating layer on the crystalline semiconductor pattern, the gate insulating layer having two first source/drain contact holes and a semiconductor pattern access hole therein;
a gate electrode on the gate insulating layer, the gate electrode being between the two first source/drain contact holes;
an interlayer insulating layer covering the gate electrode, the interlayer insulating layer having two second source/drain contact holes therein; and
source and drain electrodes on the interlayer insulating layer, each of the source and drain electrodes being insulated from the gate electrode, and having a portion connected to the crystalline semiconductor pattern through the first and second source/drain contact holes, wherein:
the semiconductor pattern access hole partially exposes the crystalline semiconductor pattern, and
the exposed crystalline semiconductor pattern is in contact with the interlayer insulating layer through the semiconductor pattern access hole.
10. The OLED display device as claimed in claim 9 , wherein:
the semiconductor pattern access hole is spaced apart from the first source/drain contact holes,
the semiconductor pattern access hole is at an upper region of the semiconductor pattern, and
the semiconductor pattern access hole corresponds to a region other than a channel region of the semiconductor pattern.
11. The OLED display device as claimed in claim 9 , wherein the gate electrode has a thickness of about 50 nm to about 200 nm.
12. The OLED display device as claimed in claim 9 , wherein the gate electrode is formed of aluminum, chromium, molybdenum, or a combination thereof.
13. The OLED display device as claimed in claim 9 , wherein the gate insulating layer includes two or more semiconductor pattern access holes therein.