Method and apparatus for integrated circuit design

1 . An integrated circuit design method comprising:

obtaining layout data of an integrated circuit; and

updating said layout data to modify said layout of said integrated circuit,

wherein said updating said layout data includes:

replacing a first via placed on an interconnection with a plurality of second vias having a size smaller than that of said first via,

wherein positions of said via origin points of said second vias on said interconnection is different from a position of a via origin point of said first via on said interconnection.

2 . The integrated circuit design method according to claim 1 , wherein said replacing includes:

specifying a forbidden region in which placement of a via are forbidden as a region of a predetermined size within which said first via origin point is positioned, and

placing said plurality of second vias in a region other than said forbidden region on said interconnection.

3 . The integrated circuit design method according to claim 2 , wherein said specifying said forbidden region includes:

specifying said forbidden region based on a via-to-via spacing criterion defined for said plurality of second vias.

4 . The integrated circuit design method according to claim 1 , wherein said replacing includes:

specifying a placement-allowed region in which said plurality of second vias are allowed to be placed, based on a via-to-via spacing criterion and a via size defined for said plurality of second vias; and

determining positions of said plurality of second vias in said placement-allowed region, based on a via-metal coverage criterion defining a minimum distance between a via and an edge of said interconnection.

5 . The integrated circuit design method according to claim 4 , wherein said replacing further includes:

modifying said positions of said plurality of second vias, when said positions of said plurality of second vias do not comply with said via-metal coverage criterion.

6 . The integrated circuit design method according to claim 4 , wherein said replacing further includes:

modifying a number of said plurality of second vias, when said positions of said plurality of second vias do not comply with said via-metal coverage criterion.

7 . A recording medium which records a program that when executed controls a computer to perform a method comprising:

obtaining layout data of an integrated circuit; and

updating said layout data to modify said layout of said integrated circuit,

wherein said updating said layout data includes:

replacing a first via placed on an interconnection with a plurality of second vias having a size smaller than that of said first via,

wherein positions of said via origin points of said second vias on said interconnection is different from a position of a via origin point of said first via on said interconnection.

8 . The recording medium according to claim 7 , wherein said replacing includes:

specifying a forbidden region in which placement of a via are forbidden as a region of a predetermined size within which said first via origin point is positioned, and

placing said plurality of second vias in a region other than said forbidden region on said interconnection.

9 . The recording medium according to claim 8 , wherein said specifying said forbidden region includes:

specifying said forbidden region based on a via-to-via spacing criterion defined for said plurality of second vias.

10 . The recording medium according to claim 7 , wherein said replacing includes:

specifying a placement-allowed region in which said plurality of second vias are allowed to be placed, based on a via-to-via spacing criterion and a via size defined for said plurality of second vias; and

determining positions of said plurality of second vias in said placement-allowed region, based on a via-metal coverage criterion defining a minimum distance between a via and an edge of said interconnection.

11 . The recording medium according to claim 10 , wherein said replacing further includes:

modifying said positions of said plurality of second vias, when said positions of said plurality of second vias do not comply with said via-metal coverage criterion.

12 . The recording medium according to claim 10 , wherein said replacing further includes:

modifying a number of said plurality of second vias, when said positions of said plurality of second vias do not comply with said via-metal coverage criterion.

13 . A method of manufacturing an integrated circuit comprising:

obtaining layout data of an integrated circuit;

updating said layout data to modify said layout of said integrated circuit;

preparing a mask by using said updated layout data; and

manufacturing said integrated circuit by using said mask,

wherein said updating said layout data includes:

replacing a first via placed on an interconnection with a plurality of second vias having a size smaller than that of said first via,

wherein positions of said via origin points of said second vias on said interconnection is different from a position of a via origin point of said first via on said interconnection.

14 . The method according to claim 13 , wherein said replacing includes:

specifying a forbidden region in which placement of a via are forbidden as a region of a predetermined size within which said first via origin point is positioned, and

placing said plurality of second vias in a region other than said forbidden region on said interconnection.

15 . The method according to claim 14 , wherein said specifying said forbidden region includes:

specifying said forbidden region based on a via-to-via spacing criterion defined for said plurality of second vias.

16 . The method according to claim 13 , wherein said replacing includes:

specifying a placement-allowed region in which said plurality of second vias are allowed to be placed, based on a via-to-via spacing criterion and a via size defined for said plurality of second vias; and

determining positions of said plurality of second vias in said placement-allowed region, based on a via-metal coverage criterion defining a minimum distance between a via and an edge of said interconnection.

17 . The method according to claim 16 , wherein said replacing further includes:

modifying said positions of said plurality of second vias, when said positions of said plurality of second vias do not comply with said via-metal coverage criterion.

18 . The method according to claim 16 , wherein said replacing further includes:

modifying a number of said plurality of second vias, when said positions of said plurality of second vias do not comply with said via-metal coverage criterion.