IP Library Granted Patent US 8,159,424
Granted Patent B2
US 8,159,424 · App. 12/458,810 · Granted Apr 17, 2012

Display device and electronic apparatus

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Quick Facts
Patent No.
US 8,159,424
App. No.
12/458,810
Granted
Apr 17, 2012
Kind
B2
Abstract

Disclosed herein is a sampling transistor in an embodiment of the present invention is kept at the on-state with a time width shorter than one horizontal cycle, during the period from the rising of a control pulse supplied from a scanner to a scan line WS to the falling of the control pulse, and samples a video signal from a signal line SL to write the video signal to a hold capacitor. The sampling transistor includes the channel region between the source and the drain and has a sandwich gate structure in which a shield that electrically shields the channel region is disposed on the other side of the channel region. This suppresses change in the threshold voltage of the sampling transistor.

Claims (84)

1. A display device comprising:

a pixel array part configured to include

scan lines disposed along rows,

signal lines disposed along columns, and

pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix; and

a drive part configured to drive the pixel array part and include

a control scanner and

a signal selector,

the control scanner sequentially applying a control pulse to the scan lines with a horizontal cycle to thereby line-sequentially scan the pixels on a row-by-row basis, the signal selector supplying a video signal to the signal lines disposed along the columns in matching with the line-sequential scanning, wherein

the pixel includes

a sampling transistor having a gate connected to the scan line and a source and a drain one of which is connected to the signal line,

a drive transistor having a gate connected to the other of the source and the drain of the sampling transistor and a source and a drain one of which is connected to a power supply,

a light-emitting element connected to the other of the source and the drain of the drive transistor, and

a hold capacitor connected between the source and the gate of the drive transistor,

the sampling transistor is kept at an on-state during a period from rising of a control pulse supplied from the control scanner to the scan line to falling of the control pulse with a time width shorter than one horizontal cycle, and samples a video signal from the signal line to write the video signal to the hold capacitor,

the sampling transistor

includes a channel region between the source and the drain and

has a sandwich gate structure in which the gate exists on one surface side of the channel region with intermediary of an insulating film and a shield that electrically shields the channel region is disposed on the other surface side of the channel region, and

the drive transistor causes a drive current dependent on a video signal written to the hold capacitor to flow to the light-emitting element for light emission.

2. The display device according to claim 1 , wherein

the shield is connected to the same potential as potential of the gate.

3. The display device according to claim 1 , wherein

the drive transistor has a shield structure different from a shield structure of the sampling transistor.

4. An electronic apparatus including

a main body part and

a display part that displays information output from the main body part, the display part comprising:

a pixel array part configured to include

scan lines disposed along rows,

signal lines disposed along columns, and

pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix; and

a drive part configured to drive the pixel array part and include

a control scanner and

a signal selector,

the control scanner sequentially applying a control pulse to the scan lines with a horizontal cycle to thereby line-sequentially scan the pixels on a row-by-row basis, the signal selector supplying a video signal to the signal lines disposed along the columns in matching with the line-sequential scanning, wherein

the pixel includes

a sampling transistor having a gate connected to the scan line and a source and a drain one of which is connected to the signal line,

a drive transistor having a gate connected to the other of the source and the drain of the sampling transistor and a source and a drain one of which is connected to a power supply,

a light-emitting element connected to the other of the source and the drain of the drive transistor, and

a hold capacitor connected between the source and the gate of the drive transistor,

the sampling transistor is kept at an on-state during a period from rising of a control pulse supplied from the control scanner to the scan line to falling of the control pulse with a time width shorter than one horizontal cycle, and samples a video signal from the signal line to write the video signal to the hold capacitor,

the sampling transistor

includes a channel region between the source and the drain and

has a sandwich gate structure in which the gate exists on one surface side of the channel region with intermediary of an insulating film and a shield that electrically shields the channel region is disposed on the other surface side of the channel region, and

the drive transistor causes a drive current dependent on a video signal written to the hold capacitor to flow to the light-emitting element for light emission.

5. A display device comprising:

pixel array means for including

scan lines disposed along rows,

signal lines disposed along columns, and

pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix; and

drive means for driving the pixel array means and including

a control scanner and

a signal selector,

the control scanner sequentially applying a control pulse to the scan lines with a horizontal cycle to thereby line-sequentially scan the pixels on a row-by-row basis, the signal selector supplying a video signal to the signal lines disposed along the columns in matching with the line-sequential scanning, wherein

the pixel includes

a sampling transistor having a gate connected to the scan line and a source and a drain one of which is connected to the signal line,

a drive transistor having a gate connected to the other of the source and the drain of the sampling transistor and a source and a drain one of which is connected to a power supply,

a light-emitting element connected to the other of the source and the drain of the drive transistor, and

a hold capacitor connected between the source and the gate of the drive transistor,

the sampling transistor is kept at an on-state during a period from rising of a control pulse supplied from the control scanner to the scan line to falling of the control pulse with a time width shorter than one horizontal cycle, and samples a video signal from the signal line to write the video signal to the hold capacitor,

the sampling transistor

includes a channel region between the source and the drain and

has a sandwich gate structure in which the gate exists on one surface side of the channel region with intermediary of an insulating film and a shield that electrically shields the channel region is disposed on the other surface side of the channel region, and

the drive transistor causes a drive current dependent on a video signal written to the hold capacitor to flow to the light-emitting element for light emission.

6. An electronic apparatus including

a main body part and

a display part that displays information output from the main body part, the display part comprising:

pixel array means for including

scan lines disposed along rows,

signal lines disposed along columns, and

pixels that are disposed at intersections of the scan lines and the signal lines and are arranged in a matrix; and

drive means for driving the pixel array means and including

a control scanner and

a signal selector,

the control scanner sequentially applying a control pulse to the scan lines with a horizontal cycle to thereby line-sequentially scan the pixels on a row-by-row basis, the signal selector supplying a video signal to the signal lines disposed along the columns in matching with the line-sequential scanning, wherein

the pixel includes

a sampling transistor having a gate connected to the scan line and a source and a drain one of which is connected to the signal line,

a drive transistor having a gate connected to the other of the source and the drain of the sampling transistor and a source and a drain one of which is connected to a power supply,

a light-emitting element connected to the other of the source and the drain of the drive transistor, and

a hold capacitor connected between the source and the gate of the drive transistor,

the sampling transistor is kept at an on-state during a period from rising of a control pulse supplied from the control scanner to the scan line to falling of the control pulse with a time width shorter than one horizontal cycle, and samples a video signal from the signal line to write the video signal to the hold capacitor,

the sampling transistor

includes a channel region between the source and the drain and

has a sandwich gate structure in which the gate exists on one surface side of the channel region with intermediary of an insulating film and a shield that electrically shields the channel region is disposed on the other surface side of the channel region, and

the drive transistor causes a drive current dependent on a video signal written to the hold capacitor to flow to the light-emitting element for light emission.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2025
From: JDI DESIGN AND DEVELOPMENT G.K.
To: MAGNOLIA BLUE CORPORATION
Reel/Frame 072039/0656 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 31, 2024
From: JOLED, INC.
To: JDI DESIGN AND DEVELOPMENT G.K.
Reel/Frame 066382/0619 →
CORRECTION BY AFFIDAVIT FILED AGAINST REEL/FRAME 063396/0671 Recorded Jun 12, 2023
From: JOLED, INC.
To: JOLED, INC.
Reel/Frame 064067/0723 →
SECURITY INTEREST Recorded Apr 20, 2023
From: JOLED, INC.
To: INCJ, LTD.
Reel/Frame 063396/0671 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 15, 2015
From: SONY CORPORATION
To: JOLED INC.
Reel/Frame 036106/0355 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 23, 2009
From: YAMAMOTO, TETSURO; YAMASHITA, JUNICHI; UCHINO, KATSUHIDE; JINTA, SEIICHIRO
To: SONY CORPORATION
Reel/Frame 023031/0189 →