Self calibrating cable for high definition digital video interface
A High Definition Multi-Media Interface (HDMI) cable may exhibit frequency dependent signal attenuation, inter symbol interference, and inter-pair skew. A boost device integrated with the cable can compensate for such impairments of the cable. A self calibrating cable with a boost device of the embodiment of the invention is described, in which parameters that control the response of the boost device are set optimally in a self-calibrating process comprising looping the boosted cable on itself through a calibration fixture that contains a calibration control device. The boost device includes pattern generators and a sampling circuit. Each high speed channel of the cable is separately tested and calibrated with the help of one of the other channels serving as a sampling channel. Additional embodiments provide for a selected replica boost device and a distinct pattern generator device in the calibration fixture.
1. A system for calibrating a high speed cable carrying a plurality of high speed data channels and a low speed control bus, the cable including an input connector and an output connector, the system comprising:
(a) a boost device including:
(i) a plurality of channel circuits, each for equalizing and amplifying a corresponding one of the high speed data channels, each channel circuit including a programmable boost circuit responsive to respective programmable parameters; and
(ii) a low speed control bus interface, interfacing the low speed control bus, for setting the programmable parameters;
(b) a calibration fixture including a connection at the output connector for receiving the boosted high speed data channels from the boost device and a connection at the input connector for transmitting a test signal to the high speed data channels of the cable; and
(c) a calibration control device, connected to the low speed control bus, for calibrating the cable by setting the programmable parameters of the boost device;
wherein the calibration fixture comprises a feed-through connection for looping the high speed data channels directly from the output connector to the input connector;
wherein each channel circuit comprises:
a pattern generator interfacing the low speed control bus interface, for generating the test signal; and
a multiplexer for alternatively selecting a signal from the programmable boost circuit in a mission mode or the test signal from the pattern generator in a calibration mode, the mission mode corresponding to an ordinary use of the high speed cable, and the calibration mode being reserved for the calibrating of the cable.
2. The system of claim 1 , wherein the boost device is embedded in the cable.
3. The system of claim 1 , wherein the boost device further includes:
a sampling circuit for sampling outputs of the programmable boost circuits; and
a sampling control circuit for monitoring the sampling circuit and for setting the programmable parameters of the respective programmable boost circuit.
4. The system of claim 3 , wherein the sampling circuit comprises:
a programmable delay for delaying an output of a first selected one of the programmable boost circuits;
a sampling circuit element for generating samples from an output of a second selected one of the programmable boost circuits clocked with the delayed output of the first selected one, wherein the samples have values of “0” and “1”; and
a means for determining an average of the values of N generated samples.
5. The system of claim 4 , wherein the sampling circuit element comprises a flip flop.
6. The system of claim 4 , wherein the means for determining the average comprises a counter for counting instances of the generated samples having the same value.
7. The system of claim 4 , wherein the sampling control circuit comprises:
a delay step counter for varying the programmable delay in predetermined delay steps;
a memory for storing the average of N generated samples for each delay step; and
a divide-by-N counter for incrementing the delay step counter to the next step after N samples have been collected.
8. The system of claim 7 , wherein the calibration control device comprises means for interpolating between the predetermined delay steps by using the stored averages.
9. The system of claim 1 , wherein the feed-through connection comprises an additional, selected boost device for receiving the high speed data channels from the output connector and transmitting the test signal to the input connector.
10. The system of claim 9 , wherein said selected boost device is another boost device, selected from manufactured boost devices and screened for high accuracy of its sampling circuit.
11. The system of claim 10 , wherein the selected boost device further includes:
another pattern generator interfacing the low speed control bus interface, for generating the test signal; and
another multiplexer predetermined for selecting said another pattern generator to generate the test signal.
12. The system of claim 11 , wherein the selected boost device further includes:
another plurality of channel circuits, each for boosting a corresponding one of the high speed data channels, each of the another plurality of channel circuits including another programmable boost circuit responsive to respective predetermined programmable parameters; and
another low speed control bus interface, interfacing the low speed control bus, for setting the predetermined programmable parameters.
13. The system of claim 12 , wherein the selected boost device further includes:
another sampling circuit for sampling outputs of said another programmable boost circuits; and
another sampling control circuit for monitoring said another sampling circuit.
14. The system of claim 13 , wherein said another sampling circuit comprises:
another programmable delay for delaying an output of a first selected one of said another programmable boost circuits;
another sampling circuit element for generating samples from an output of a second selected one of said another programmable boost circuits clocked with the delayed output of the first selected one, wherein the samples have values of “0” and “1”; and
another means for determining an average of the values of N generated samples.
15. The system of claim 14 , wherein said another sampling circuit element comprises another flip flop.
16. The system of claim 14 , wherein said another means for determining the average comprises another counter for counting instances of the generated samples having the same value.
17. The system of claim 14 , wherein said another sampling control circuit comprises:
another delay step counter for varying the another programmable delay in predetermined delay steps;
another memory for storing the average of N generated samples for each delay step;
another divide-by-N counter for incrementing the another delay step counter to the next step after N samples have been collected.
18. The system of claim 17 , wherein the calibration control device comprises means for interpolating between the predetermined delay steps by using the averages stored in said another memory.
19. The system of claim 1 , wherein the calibration fixture comprises a receiving boost device for receiving the high speed data channels from the output connector and a transmit chip for transmitting the test signal to the input connector.
20. The system of claim 19 , wherein the receiving boost device is yet another boost device, selected from manufactured boost devices and screened for high accuracy of its sampling circuit.
21. The system of claim 20 , wherein the receiving boost device includes:
yet another plurality of channel circuits, each for boosting a corresponding one of the high speed data channels, each of the yet another plurality of channel circuits including yet another programmable boost circuit responsive to predetermined programmable parameters; and
yet another low speed control bus interface, interfacing the low speed control bus, for setting the predetermined programmable parameters.
22. The system of claim 21 , wherein the receiving boost device further includes:
yet another sampling circuit for sampling outputs of said yet another programmable boost circuits; and
yet another sampling control circuit for monitoring said yet another sampling circuit.
23. The system of claim 22 , wherein said yet another sampling circuit comprises:
yet another programmable delay for delaying an output of a first selected one of said yet another programmable boost circuits; and
yet another sampling circuit element for generating samples from an output of a second selected one of said yet another programmable boost circuits clocked with the delayed output of the first selected one, wherein the samples have values of “0” and “1”; and
yet another means for determining an average of the values of N generated samples.
24. The system of claim 23 , wherein said yet another sampling circuit element comprises yet another flip flop.
25. The system of claim 23 , wherein said yet another means for determining the average comprises yet another counter for counting instances of the generated samples having the same value.
26. The system of claim 23 , wherein said yet another sampling control circuit comprises:
yet another delay step counter for varying the yet another programmable delay in predetermined delay steps;
yet another memory for storing the average of N generated samples for each delay step;
yet another divide-by-N counter for incrementing the yet another delay step counter to the next step after N samples have been collected.
27. The system of claim 26 , wherein the calibration control device comprises means for interpolating between the predetermined delay steps by using the averages stored in said yet another memory.
28. A method of calibrating a high speed cable carrying a plurality of high speed data channels and a low speed control bus, the cable including an input connector, an output connector, and an embedded boost device, the method comprising:
(a) in the embedded boost device, generating a test signal in a pattern generator;
(b) by a calibration control device, selecting a boosted signal in a high speed data channel in a mission mode or the test signal in a calibration mode, the mission mode corresponding to an ordinary use of the high speed cable, and the calibration mode being reserved for the calibrating of the cable;
in the calibration mode:
(c) looping the test signal in the high speed data channel from the embedded boost device to the output connector, from the output connector to the input connector outside of the cable, and back through the cable to the embedded boost device for equalizing and amplifying the test signal with programmable parameters of the boost device;
(d) in the embedded boost device, setting programmable parameters for use in the mission mode based on the programmable parameters selected in the calibration mode, comprising:
(i) sampling the equalized and amplified test signal in a sampling circuit of the boost device; and
(ii) setting the programmable parameters by monitoring the sampling circuit with the calibration control device connected to the boost device over the low speed control bus, thereby calibrating the cable.
29. The method of claim 28 , the step (i) further comprises:
(e) generating a sampling signal in another high speed data channel;
(f) looping the sampling signal in the another high speed data channel from the boost device to the output connector, from the output connector to the input connector outside of the cable, and back through the cable to the embedded boost device for equalizing and amplifying the sampling signal with programmable parameters of the boost device;
(g) delaying the equalized and amplified sampling signal; and
(h) sampling the equalized and amplified test signal with the delayed equalized and amplified sampling signal to generate samples.
30. The method of claim 29 , wherein the step (h) further comprises counting instances of the generated samples having the same value.
31. The method of claim 30 , wherein:
the step (g) comprises varying a programmable delay in predetermined delay steps; and
the step (h) further comprises storing averages of generated samples for each delay step in a memory.
32. The method of claim 31 , wherein the step (g) further comprises interpolating between the predetermined delay steps by using the stored averages.
33. The method of claim 28 , further comprising changing the programmable parameters, and selecting the programmable parameters which correspond to the lowest distortion of the equalized and amplified test signal.