Semiconductor device manufacturing method
View Patent ↗A semiconductor device manufacturing method includes: providing a laminated member in which at least a first GaAs layer, an InAlGaAs layer and a second GaAs layer are laminated on or above a substrate in this order; and etching the second GaAs layer using the InAlGaAs layer as an etching stopper layer. A ratio of In:Al of the InAlGaAs layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs layer is in a range of approximately 1.5:8.5 to approximately 5:5.
1. A semiconductor device manufacturing method, comprising:
providing a laminated member in which at least an AlGaAs electron donating layer or an AlGaAs Schottky layer, a GaAs gate-buried layer, an InAlGaAs etching stopper layer, and a GaAs contact layer are laminated on or above a substrate in this order;
etching the GaAs contact layer to form a first through hole;
etching the InAlGaAs etching stopper layer to form a second through hole having approximately the same size as the first through hole;
etching the GaAs gate-buried layer to form a third through hole in the first and second through holes, the third through hole being smaller than the first through hole; and
forming an electrode in the first and second through holes, wherein
a ratio of In:Al of the InAlGaAs etching stopper layer is in a range of approximately 4:6 to approximately 6:4 and a ratio of (In+Al):Ga of the InAlGaAs etching stopper layer is in a range of approximately 1.5:8.5 to approximately 5:5.
2. A semiconductor device manufacturing method according to claim 1 , wherein an etchant for etching the GaAs contact layer is a mixed liquid of an organic acid or a salt thereof, oxygenated water and water.
3. A semiconductor device manufacturing method according to claim 1 , wherein an etchant for etching the GaAs contact layer is an etchant with which an etching rate of the InAlGaAs etching stopper layer is equal to or less than 1/50 of an etching rate of the GaAs contact layer.
4. A semiconductor device manufacturing method according to claim 1 , wherein the GaAs gate-buried layer is an undoped GaAs gate-buried layer or an AlGaAs gate-buried layer including Al at a low concentration.