Constant current read mode or constant current data retention mode nonvolatile memory device
View Patent ↗A non-volatile semiconductor memory circuit capable of improving data retention characteristics and decreasing an area thereof comprises a constant current circuit and a non-volatile memory cell connected in series. A connection point between the constant current source and the non-volatile memory cell is selected to be an output to thereby enable writing, in a reading mode or a retention mode, in the non-volatile memory cell which is in a write state. The non-volatile semiconductor memory circuit includes a power supply for data reading and retaining and a power supply for data rewriting which are provided independently, and a transistor connected between the output and the power supply for data rewriting, in which the transistor is brought into conduction state when data is rewritten.
1. A non-volatile semiconductor memory circuit, comprising:
a non-volatile memory cell having an erase state in which a threshold voltage is low and a write state in which the threshold voltage is high to thereby store data;
a constant current circuit connected in series with the non-volatile memory cell; and
a connection point between the non-volatile memory cell and the constant current circuit being set to be an output;
wherein, in a reading mode or a retention mode, in which a voltage is applied to the non-volatile memory cell, the following relationship is satisfied:
I WRITE <I CONST <I ERASE ,
where a saturation current flowing through the non-volatile memory cell in the erase state is represented by I ERASE , a saturation current flowing through the non-volatile memory cell in the write state is represented by I WRITE , and a constant current provided from the constant current circuit is represented by I CONST .
2. The non-volatile semiconductor memory circuit according to claim 1 , wherein in one of the reading mode and the retention mode:
in a case where the non-volatile memory cell is in the erase state, a voltage applied between a source and a drain of the non-volatile memory cell is made to be close to 0 V, to thereby prevent writing in the non-volatile memory cell which is in the erase state; and
in a case where the non-volatile memory cell is in the write state, the voltage applied between the source and the drain of the non-volatile memory cell is made to be close to a power supply voltage higher than another power supply voltage, to thereby allow writing in the non-volatile memory cell which is in the write state by hot electrons.
3. The non-volatile semiconductor memory circuit according to claim 1 , further comprising:
a power supply line used in the reading mode and the retention mode;
another power supply line which is provided separately from the power supply line and is used in data rewriting of the non-volatile memory cell; and
a transistor provided between the output and the another power supply line used in the data rewriting of the non-volatile memory cell;
wherein the transistor is brought into conduction state at a time of the data rewriting of the non-volatile memory cell.
4. The non-volatile semiconductor memory circuit according to claim 1 ; wherein the constant current flows constantly through a circuit formed of the constant current circuit and the non-volatile memory cell which are connected in series while a power supply voltage is applied to the circuit.
5. The non-volatile semiconductor memory circuit according to claim 1 ; wherein the constant current circuit comprises a MOS transistor which is in a saturated operating state.