DC biasing circuit for a metal oxide semiconductor transistor
A method for biasing a MOS transistor includes AC coupling an input signal from an amplifier stage to a gate of the MOS transistor. The method includes connecting a pair of diodes in an opposing parallel configuration to a bias transistor and a current source. Further, the method includes generating a DC bias voltage through the bias transistor and the current source. The method also includes clamping the voltage at drain of the bias transistor to a fixed voltage by a clamping circuit. Further, the method includes coupling the DC bias voltage to the gate of the MOS transistor through the pair of diodes.
1. A method of biasing a metal oxide semiconductor (MOS) transistor, the method comprising:
AC coupling an input signal to a gate of the MOS transistor; and
generating a DC bias voltage at the gate of the MOS transistor from a DC current source through a parallel combination of a minor transistor, a forward-biased diode, and a reverse-biased diode stack, a DC voltage clamp being connected between the DC current source and a source of the MOS transistor, the combination of the forward-biased diode and the reverse-biased diode stack having a DC resistance value exceeding one gigaohm.
2. The method of claim 1 , wherein the reverse-biased diode stack comprises three diodes.
3. A DC biasing circuit for a Metal Oxide Semiconductor (MOS) transistor, the circuit comprising:
a first MOS transistor having a source connected to a first power supply terminal, a drain connected to an output node, and a gate;
a load connected between the output node and a second power supply terminal;
a current source connected between the second power supply terminal and a bias node;
a first diode in a forward-biased connection between the bias node and the gate;
a diode stack of a plurality of diodes in series in a reverse-biased connection between the bias node and the gate;
a voltage clamp connected between the bias node and the source of the first MOS transistor; and
a second MOS transistor having a source connected to the first transistor source, a gate connected to the first transistor gate, and a drain connected to the bias node, the combination of the first diode and the diode stack having a DC resistance value exceeding one gigaohm.
4. The DC biasing circuit of claim 3 , wherein the voltage clamp comprises a transistor with a drain and a gate shorted together.
5. The DC biasing circuit of claim 3 , wherein the diode stack comprises three diodes.
6. The DC biasing circuit of claim 3 , wherein the load comprises a resistor.
7. The DC biasing circuit of claim 3 further comprising a capacitor connected to the gate of the first transistor.