Packet processor, packet control method, and packet control program
View Patent ↗A packet processor having one or two or more packet processing units is provided with a packet detector which detects whether or not a packet exists in a packet processing unit, and outputs a packet detection signal indicating a result of the detection, and a clock frequency controller which controls a clock to be supplied to the packet processing unit based on the packet detection signal.
1. A packet processor comprising:
a packet processing unit;
a packet detector for detecting whether or not a packet exists in the packet processing unit and outputting a packet detection signal indicating a result of the detection; and
a clock frequency controller for controlling a frequency of a clock supplied to the packet processing unit based on the packet detection signal.
2. The packet processor as claimed in claim 1 , wherein the packet detector monitors packets input to and output from the packet processing unit to detect whether or not a packet exists in the packet processing unit.
3. The packet processor as claimed in claim 1 , comprising an input-side packet buffer which accumulates a packet input externally and outputs a packet detection signal indicating whether or not a packet is accumulated therein.
4. The packet processor as claimed in claim 1 , comprising an output-side packet buffer which accumulates a packet having undergone predetermined processing in the packet processing unit, and outputs a packet detection signal indicating whether or not a packet is accumulated therein.
5. The packet processor as claimed in claim 1 , wherein the clock frequency controller comprises:
a clock frequency control instruction unit which receives the packet detection signal, generates a clock frequency control signal based on the received packet detection signal, and outputs the generated clock frequency control signal; and
a clock frequency control unit for controlling a frequency of a clock supplied to the packet processing unit based on the clock frequency control signal.
6. The packet processor as claimed in claim 5 , wherein when no packet exists in the packet processing unit, the clock frequency control instruction unit generates a clock frequency control signal indicating that the frequency of the clock supplied to the packet processing unit is to be controlled and outputs the generated clock frequency control signal.
7. The packet processor as claimed in claim 5 , wherein when a packet exists neither in the packet processing unit nor in a processing unit preceding the packet processing unit, the clock frequency control instruction unit generates a clock frequency control signal indicating that the frequency of the clock supplied to the packet processing unit is to be controlled and outputs the generated clock frequency control signal.
8. The packet processor as claimed in claim 5 , further comprising:
a setting information input unit for receiving information relating to clock frequency control; and
a clock frequency control information setting unit for sending the received information to the clock frequency control unit.
9. A packet control method for performing predetermined processing on an input packet and outputting the processed packet, the method comprising:
detecting whether or not a packet exists in a packet processing unit for performing the predetermined processing; and
performing a frequency squeezing control on a clock supplied to the packet processing unit when no packet exists in the packet processing unit.
10. The packet control method as claimed in claim 9 , further comprising:
detecting whether or not a packet exists in a packet processing unit preceding the relevant processing unit; and
performing a frequency squeezing control on a clock supplied to the relevant packet processing unit when a packet exists both neither in the relevant packet processing unit nor in the processing unit preceding the relevant packet processing unit.
11. A computer readable non-transitory medium embodied thereon a packet control program for causing a packet processor to perform predetermined processing on a packet input thereto and to output the processed packet, wherein the predetermined processing comprises:
detecting whether or not a packet exists in the packet processing unit for performing the predetermined processing; and
performing a frequency squeezing control on a clock supplied to the packet processing unit when no packet exists in the packet processing unit.
12. The computer readable non-transitory medium as claimed in claim 11 , wherein the packet control program causes a packet processor to perform processing comprising:
detecting whether or not a packet exists in a packet processing unit preceding the relevant processing unit; and
performing a frequency squeezing control on a clock supplied to the relevant packet processing unit when a packet exists neither in the relevant packet processing unit nor in the packet processing unit preceding the relevant processing unit.