Timer for low-power and high-resolution with low bits derived from set of phase shifted clock signals

1. An electronic device, comprising:

a counter driven by a first input clock signal for counting clock cycles of the input clock signal and providing a predetermined set of most significant bits of a count;

a clock signal generating stage driven by a second input clock signal for generating a first set of phase shifted clock signals having m different phases; and

a code converter stage receiving the set of phase shifted clock signals for converting m states of the set of phase shifted clock signals into n least significant bits of the count, whereby the count consists of the predetermined set of most significant bits and the n least significant bits.

2. The electronic device according to claim 1 , further comprising:

a register for storing the states of the first set of phase shifted clock signals.

3. The electronic device according to claim 1 , wherein:

the clock signal generating stage includes a first chain of delay elements, each delay element having a delay smaller than a clock period of the input clock signal, a first delay element having an input receiving the input clock signal and an output, each other delay element having an input connected to an output of a prior delay element and an output, the first chain of delay elements providing the first set of m phase shifted clock signals at respective outputs.

4. The electronic device according to claim 3 , wherein:

the first chain of delay elements is a ring oscillator.

5. The electronic device according to claim 3 , wherein:

each delay element has a delay of t T equal to 2 (−k) /f IN , where k is an integer greater than 0 and f IN is the frequency of the input clock signal.

6. The electronic device according to claim 5 , wherein:

the number m of delayed clock signals is equal to 2 k .

7. The electronic device according to claim 1 , further comprising:

a phase control loop coupled to synchronize the first set of phase shifted signals with the input clock signal.

8. The electronic device according to claim 1 , further comprising:

a frequency control loop coupled to synchronize the first set of phase shifted signals to the input clock signal.

9. The electronic device according to claim 1 , wherein:

the clock generating stage includes a flip-flop outputting a more significant bit of the count.

10. The electronic device according to claim 9 , wherein:

the flip-flop has an input receiving one of the first set of phase shifted clock signals.

11. The electronic device according to claim 1 , wherein:

the clock signal generating stage further generates a second set of m phase shifted clock signals; and

the electronic device further comprises a controlling means switching between the first set of phase shifted clock signals and the second set of phase shifted clock signials.

12. The electronic device according to claim 1 , further comprising:

a decoding stage coupled to an output of the clock signal generating stage selecting one of the phase shifted clock signals to providing an edge of a pulse of a pulse width modulated signal within a period of the clock signal.

13. The electronic device of claim 1 , wherein:

said first clock signal is said second clock signal.

14. The electronic device of claim 1 , wherein:

said first clock signal is one of the first set of phase shifted clock signals.

15. The electronic device of claim 1 , further comprising:

a switch having a first input receiving the second clock signal, a second input receiving one of the first set of phase shifted clock signals and an output connected to the counter, whereby the first clock signal is selected as the second clock signal or the one of the first set of phase shifted clock signals.

16. A method of providing a timer value comprising:

counting clock cycles of a first input clock signal so as to receive a count representing a plurality of most significant bit values of the timer value;

generating a set of m phase shifted clock signals from a second input clock signal, each of the phase shifted clock signals being delayed with respect to another phase shifted clock signal by less than a clock period of the second input clock signal;

determining a plurality of n least significant bit values based on the states of the phase shifted clock signals of the set of phase shifted clock signals; and

composing the timer value by concatenating the n least significant bit values and the plurality of most significant bit values.

17. The method of providing a timer value of claim 16 , further comprising:

selecting one of the phase shifted clock signals; and

adjusting an edge of a pulse of a pulse width modulated signal within a period of the clock signal using the selected clock signal.

18. The method of claim 16 , wherein:

the first clock signal is the second clock signal.

19. The method of claim 16 , wherein:

the first clock signal is one of the set of m phase shifted clock signals.

20. The method of claim 16 , wherein:

the first clock signal is a selectable one of the second clock signal or the one of the set of m phase shifted clock signals.